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Change subject: mb, soc: Add the SPD_CACHE_ENABLE
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/romstage.c:
https://review.coreboot.org/c/coreboot/+/62294/comment/428b92c3_9d4ada8e
PS4, Line 25: if (dimms_changed) {
Can we add config(CONFIG_MEMORY_SODIMM) check here?
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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/62192/comment/ed820f88_a8223270
PS1, Line 130: MAX_RETRY_EOP_MSG
> correct,
Don't you need change here cse_disable_mei_bus() as well to include retries?
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Change subject: mb, soc: Add the SPD_CACHE_ENABLE
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/62192/comment/1a26aa82_c8ddd420
PS1, Line 130: MAX_RETRY_EOP_MSG
> Sure, it sounds like tl;dr the retries are only required for security-critical commands, like bus di […]
correct,
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Change subject: mb, soc: Add the SPD_CACHE_ENABLE
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS2:
> > >True, we need to pass the FSPM_UPD structure rather soc config structure alone. […]
Thanks Subrata. Let's close this thread.
File src/mainboard/google/brya/romstage.c:
https://review.coreboot.org/c/coreboot/+/62294/comment/d74068cf_5a1aa693
PS2, Line 24: memcfg_init(m_cfg, mem_config, &spd_info,
: half_populated, &dimms_changed);
> ok, i will update it later. BTW, is there any plan to modify this doc? https://www.coreboot. […]
Update the update with 96 col per line 😊
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62294
to look at the new patch set (#4).
Change subject: mb, soc: Add the SPD_CACHE_ENABLE
......................................................................
mb, soc: Add the SPD_CACHE_ENABLE
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org>
---
M src/mainboard/google/brya/romstage.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/shadowmountain/romstage.c
M src/mainboard/prodrive/atlas/romstage_fsp_params.c
M src/soc/intel/alderlake/include/soc/meminit.h
M src/soc/intel/alderlake/meminit.c
M src/soc/intel/common/block/include/intelblocks/meminit.h
M src/soc/intel/common/block/memory/Kconfig
M src/soc/intel/common/block/memory/meminit.c
M src/soc/intel/tigerlake/meminit.c
10 files changed, 80 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/62294/4
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Change subject: Documentation/mainboard: Add QEMU POWER9 to index site
......................................................................
Patch Set 3: Code-Review+1
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Change subject: Documentation: Fix spelling of "QEMU"
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62450/comment/27bdc315_8fe9fc85
PS3, Line 7: Documentation: Fix spelling of "QEMU"
Capitalize QEMU
https://review.coreboot.org/c/coreboot/+/62450/comment/62ea7557_37f35481
PS3, Line 8:
Please reference the source.
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Change subject: Documentation: Fix spelling of "Supermicro"
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62448/comment/bbae0b4a_069468fe
PS1, Line 7: Fix spelling of "Supermicro"
Spell Supermicro lowercase
https://review.coreboot.org/c/coreboot/+/62448/comment/6005813a_621a3d31
PS1, Line 8:
Please reference the source, that it’s the official spelling.
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 sku
......................................................................
mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 sku
Update TDP PL1, PL2, and PL4 for U28 sku
BUG=b:221338290
TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c
---
M src/mainboard/google/brya/variants/kano/overridetree.cb
M src/mainboard/google/brya/variants/kano/ramstage.c
2 files changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62466/2
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