coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb, soc: Add the SPD_CACHE_ENABLE
by Zhuohao Lee (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62294 ) Change subject: mb, soc: Add the SPD_CACHE_ENABLE ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > > Hi Subrata/Tim, […] >True, we need to pass the FSPM_UPD structure rather soc config structure alone. if you have time constraint, please go with current approach and I will make it proper in coming days. We're going to clean up the brask issue and we will need this CL before the end of the this week. Will you be able to make the change before that? If so, i think we can wait for it 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/62294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Gerrit-Change-Number: 62294 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 05:20:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb, soc: Add the SPD_CACHE_ENABLE
by Subrata Banik (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62294 ) Change subject: mb, soc: Add the SPD_CACHE_ENABLE ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Hi Subrata/Tim, > > Sorry, i could be misunderstand your meaning. I thought the original request is asking to move the below full training setting to the function read_spd_dimm() https://review.coreboot.org/c/coreboot/+/62294/3/src/soc/intel/common/block… : > > ``` > if (dimms_changed) { > memupd->FspmArchUpd.NvsBufferPtr = 0; > memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; > } > ``` > Thats correct, I expected this to handle inside https://review.coreboot.org/c/coreboot/+/62294/3/src/soc/intel/common/block… itself. > However, that change will require the FSPM_UPD *memupd be passing to the function mem_populate_channel_data() in order to pass it to the read_spd_dimm(). But the mem_populate_channel_data() is a common api and will require the other intel soc change(eg. tigerlake). https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… > > Do we need to change it or could we just apply the current approach? True, we need to pass the FSPM_UPD structure rather soc config structure alone. if you have time constraint, please go with current approach and I will make it proper in coming days. -- To view, visit https://review.coreboot.org/c/coreboot/+/62294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Gerrit-Change-Number: 62294 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 04:51:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb, soc: Add the SPD_CACHE_ENABLE
by Zhuohao Lee (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62294 ) Change subject: mb, soc: Add the SPD_CACHE_ENABLE ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Wait sorry I'm going crazy, you already did this? https://review.coreboot. […] Hi Subrata/Tim, Sorry, i could be misunderstand your meaning. I thought the original request is asking to move the below full training setting to the function read_spd_dimm() https://review.coreboot.org/c/coreboot/+/62294/3/src/soc/intel/common/block… : ``` if (dimms_changed) { memupd->FspmArchUpd.NvsBufferPtr = 0; memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; } ``` However, that change will require the FSPM_UPD *memupd be passing to the function mem_populate_channel_data() in order to pass it to the read_spd_dimm(). But the mem_populate_channel_data() is a common api and will require the other intel soc change(eg. tigerlake). https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… Do we need to change it or could we just apply the current approach? -- To view, visit https://review.coreboot.org/c/coreboot/+/62294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Gerrit-Change-Number: 62294 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 04:47:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62290 ) Change subject: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test ...................................................................... Patch Set 7: (1 comment) File src/soc/mediatek/mt8186/rtc.c: https://review.coreboot.org/c/coreboot/+/62290/comment/03f3a7e5_649bafc2 PS6, Line 16: ((1 << 13) - (1 << 8)) > Can we use the GENMASK() macro? this definition is not used. I remove them in this patch: https://review.coreboot.org/c/coreboot/+/62457 -- To view, visit https://review.coreboot.org/c/coreboot/+/62290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Gerrit-Change-Number: 62290 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 03:44:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: remove RTC_GPIO_USER_MASK
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62457 ) Change subject: soc/mediatek: remove RTC_GPIO_USER_MASK ...................................................................... soc/mediatek: remove RTC_GPIO_USER_MASK RTC_GPIO_USER_MASK is not used in any drivers, so we remove them. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd --- M src/soc/mediatek/common/rtc_mt6359p.c M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8183/rtc.c M src/soc/mediatek/mt8186/rtc.c 4 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/62457/1 diff --git a/src/soc/mediatek/common/rtc_mt6359p.c b/src/soc/mediatek/common/rtc_mt6359p.c index b5c381b..2b5611b 100644 --- a/src/soc/mediatek/common/rtc_mt6359p.c +++ b/src/soc/mediatek/common/rtc_mt6359p.c @@ -9,8 +9,6 @@ #include <soc/rtc_common.h> #include <timer.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - static struct pmif *pmif_arb = NULL; void rtc_read(u16 addr, u16 *rdata) diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index d60f722..326a951 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -7,8 +7,6 @@ #include <soc/pmic_wrap.h> #include <types.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* initialize rtc related gpio */ static bool rtc_gpio_init(void) { diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index e90aa9d..40830b0 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -8,8 +8,6 @@ #include <soc/pmic_wrap.h> #include <timer.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* initialize rtc setting of using dcxo clock */ static bool rtc_enable_dcxo(void) { diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 7e38742..528f42b 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -13,8 +13,6 @@ #include <soc/pmic_wrap.h> #include <timer.h> -#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* Initialize RTC setting of using DCXO clock */ static bool rtc_enable_dcxo(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/62457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Gerrit-Change-Number: 62457 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62290 to look at the new patch set (#7). Change subject: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test ...................................................................... soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test The XTAL 26MHz test failed on krabby, so we adjust RTC capid from default value 0x88 to 0xC0 for MT8186. We also add a new log message to show the capid value which is read from MT6366. This implementation is according to chapter 5.13 in MT8186 Functional Specification. BUG=b:218439447 TEST=set capid to 0xc0. TEST=XTAL 26MHz test passed. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 --- M src/soc/mediatek/mt8186/include/soc/rtc.h M src/soc/mediatek/mt8186/rtc.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/62290/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Gerrit-Change-Number: 62290 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/vell: Change AMP driver setting
by Robert Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Kevin Chiu, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Nick Vaccaro, Name of user not set #1004174, Shon Wang. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60331 ) Change subject: mb/google/brya/var/vell: Change AMP driver setting ...................................................................... Patch Set 33: (3 comments) File src/mainboard/google/brya/variants/vell/overridetree.cb: https://review.coreboot.org/c/coreboot/+/60331/comment/bf2b58f8_af3beb92 PS32, Line 173: device ref i2c0 on > these are all missing the entry to set them to external boost: […] Done https://review.coreboot.org/c/coreboot/+/60331/comment/170f0cf6_8b12d34a PS32, Line 177: register "boost_peak_milliamp" = "4500" : register "boost_ind_nanohenry" = "BOOST_IND_1000_NH" : register "boost_cap_microfarad" = "24" > these aren't required for external boost. […] Done https://review.coreboot.org/c/coreboot/+/60331/comment/d6a2dcc1_ebecff95 PS32, Line 182: register "gpio_src_select[0]" = "GPIO_SRC_HIGH_IMPEDANCE" > the driver will override this anyway, so not critical, but gpio_src_select[0] should be GPIO_SRC_GPI […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c Gerrit-Change-Number: 60331 Gerrit-PatchSet: 33 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Name of user not set #1004174 Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Name of user not set #1004174 Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 03:19:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1004174 Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Yu-Ping Wu (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Paul Menzel, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 16: (2 comments) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/80663458_b78249c5 PS16, Line 109: /* LPDDR4X */ Could be removed now. https://review.coreboot.org/c/coreboot/+/61334/comment/06fdade5_250ff836 PS16, Line 111: mem_chip channel array: 2 Let's wait for the discussion on CB:59193. -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 16 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 03:16:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Change AMP driver setting
by Robert Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Kevin Chiu, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Robert Chen, Nick Vaccaro, Shon Wang. Robert Chen has uploaded a new patch set (#33) to the change originally created by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/60331 ) Change subject: mb/google/brya/var/vell: Change AMP driver setting ...................................................................... mb/google/brya/var/vell: Change AMP driver setting 1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4 2.Select CS35l53 AMP driver for Vell variant. Signed-off-by: Shon.Wang <shon.wang(a)quanta.corp-partner.google.com> Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/vell/overridetree.cb 3 files changed, 44 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60331/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/60331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c Gerrit-Change-Number: 60331 Gerrit-PatchSet: 33 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Name of user not set #1004174 Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26MHz test
by Yu-Ping Wu (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62290 ) Change subject: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26MHz test ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8186/rtc.c: https://review.coreboot.org/c/coreboot/+/62290/comment/06484073_21c5381b PS6, Line 16: ((1 << 13) - (1 << 8)) Can we use the GENMASK() macro? -- To view, visit https://review.coreboot.org/c/coreboot/+/62290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Gerrit-Change-Number: 62290 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 03:12:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022