coreboot-gerrit March 2022

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Change in coreboot[master]: sc7280: Add PCIe host controller driver
by Shelley Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Ravi kumar, Furquan Shaikh, Paul Menzel, Ravi Kumar Bokka, Julius Werner, Prasad Malisetty, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe host controller driver ...................................................................... Patch Set 66: (1 comment) File src/soc/qualcomm/sc7280/Makefile.inc: https://review.coreboot.org/c/coreboot/+/53902/comment/b0066f78_a5f47d55 PS66, Line 47: ramstage-y does this need to be ramstage-$(CONFIG_PCI) since we need to make sure that PCI support is enabled in the Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 66 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 06:46:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb, soc: Add the SPD_CACHE_ENABLE
by Subrata Banik (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62294 ) Change subject: mb, soc: Add the SPD_CACHE_ENABLE ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > >True, we need to pass the FSPM_UPD structure rather soc config structure alone. if you have time constraint, please go with current approach and I will make it proper in coming days. > > We're going to clean up the brask issue and we will need this CL before the end of the this week. Will you be able to make the change before that? I'm not sure if able to pick this before EOW. If you have priority, please go ahead and I will pick this work after CL lands. > If so, i think we can wait for it 😊 Please don't wait for me, just to be at safe side 😊 from your work priority. -- To view, visit https://review.coreboot.org/c/coreboot/+/62294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Gerrit-Change-Number: 62294 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 06:44:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in blobs[master]: soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10
by Hung-Te Lin (Code Review) 01 Mar '22

01 Mar '22

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/blobs/+/62327 ) Change subject: soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10 ...................................................................... soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10 The SRCLKENA0 is not pulled down when suspending. The root cause is that 26MHz clock is not disabled when suspending, so we update SPM firmware to fix this issue. TEST=verify 26MHz clock off using the oscilloscope. BUG=b:215639203 Signed-off-by: Jason-ch Chen <jason-ch.chen(a)mediatek.com> Change-Id: Iccaea858ff37cc3934c9a9a64bce7edf7cb0fbf1 --- M soc/mediatek/mt8186/spm_firmware.bin M soc/mediatek/mt8186/spm_firmware.bin.md5 M soc/mediatek/mt8186/spm_release_notes.txt 3 files changed, 4 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Verified; Looks good to me, approved diff --git a/soc/mediatek/mt8186/spm_firmware.bin b/soc/mediatek/mt8186/spm_firmware.bin index 7e0ca8d..c1b2804 100644 --- a/soc/mediatek/mt8186/spm_firmware.bin +++ b/soc/mediatek/mt8186/spm_firmware.bin Binary files differ diff --git a/soc/mediatek/mt8186/spm_firmware.bin.md5 b/soc/mediatek/mt8186/spm_firmware.bin.md5 index 910cf06..7d43cf2 100644 --- a/soc/mediatek/mt8186/spm_firmware.bin.md5 +++ b/soc/mediatek/mt8186/spm_firmware.bin.md5 @@ -1 +1 @@ -7db456c2374b3a76daa9e6f0f2b4fd71 *spm_firmware.bin +265ce2c876ca4d6d7febe9cbcc2dd005 *spm_firmware.bin diff --git a/soc/mediatek/mt8186/spm_release_notes.txt b/soc/mediatek/mt8186/spm_release_notes.txt index 7d72463..568e414 100644 --- a/soc/mediatek/mt8186/spm_release_notes.txt +++ b/soc/mediatek/mt8186/spm_release_notes.txt @@ -1,4 +1,7 @@ ** Build from MediaTek Internal ** +# pcm_suspend_v0215_v10 +1. Disable 26MHz clock while suspending. + # pcm_suspend_mp_v1109 1. SPM suspend can turn 26M clock off when system goes into suspend. -- To view, visit https://review.coreboot.org/c/blobs/+/62327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: Iccaea858ff37cc3934c9a9a64bce7edf7cb0fbf1 Gerrit-Change-Number: 62327 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7280: Add PCIe host controller driver
by Shelley Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Ravi kumar, Furquan Shaikh, Paul Menzel, Ravi Kumar Bokka, Julius Werner, Prasad Malisetty, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe host controller driver ...................................................................... Patch Set 66: (2 comments) Patchset: PS66: I don't see any changes to src/soc/qualcomm/sc7280/Kconfig, as mentioned in: https://review.coreboot.org/c/coreboot/+/58668/4/src/soc/qualcomm/sc7280/Kc… You need to add PCI (because you are using PCI support) and you need to set NO_ECAM_MMCONF_SUPPORT because you are not using ECAM. Once you set those Kconfigs, you'll start to see compilation errors due to pci_map_bus not being defined. This should be your atu mapping function that you defined in pcie_host.c. File src/soc/qualcomm/sc7280/pcie_host.c: https://review.coreboot.org/c/coreboot/+/53902/comment/9d4d3c3a_f803c708 PS66, Line 367: qcom_dw_pcie_prog_outbound_atu This is the main address mapping function, correct? Then this needs to be renamed pci_map_bus (or create a wrapper around this), as that needs to be defined if you are not using the ECAM method. The function prototype is defined in pci_mmio_cfg.h: volatile union pci_bank *pci_map_bus(pci_devfn_t dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 66 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 06:35:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
by Yu-Ping Wu (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62290 ) Change subject: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Gerrit-Change-Number: 62290 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 06:16:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: remove RTC_GPIO_USER_MASK
by Yu-Ping Wu (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62457 ) Change subject: soc/mediatek: remove RTC_GPIO_USER_MASK ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Gerrit-Change-Number: 62457 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 06:15:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in blobs[master]: soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/62327 ) Change subject: soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10 ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: @hung-te, could you help to merge this patch? Thanks! -- To view, visit https://review.coreboot.org/c/blobs/+/62327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: Iccaea858ff37cc3934c9a9a64bce7edf7cb0fbf1 Gerrit-Change-Number: 62327 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 06:04:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 sku
by David Wu (Code Review) 01 Mar '22

01 Mar '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62466 ) Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 sku ...................................................................... mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 sku Update TDP PL1, PL2, and PL4 for U28 sku BUG=b:221338290 TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c --- M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/kano/ramstage.c 2 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62466/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 5fbeb3c..2685c59 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -63,6 +63,18 @@ }, }" + register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 43, + .tdp_pl4 = 105, + }" + + register "power_limits_config[ADL_P_682_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 43, + .tdp_pl4 = 105, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -119,14 +131,14 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 18000, - .max_power = 28000, + .max_power = 20000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { .min_power = 40000, - .max_power = 40000, + .max_power = 43000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c index 9b26cbb..2d4a53f 100644 --- a/src/mainboard/google/brya/variants/kano/ramstage.c +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -7,8 +7,8 @@ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 40000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 40000, 43000, 105000 }, }; void variant_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/62466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c Gerrit-Change-Number: 62466 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
by Casper Chang (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai. Hello Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62465 to look at the new patch set (#3). Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked ...................................................................... mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after warm reboot. Config GPP_B3 unlocked to make reboot works on primus. BUG=b:221488504 TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage test reboot 30 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62465/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Gerrit-Change-Number: 62465 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
by Casper Chang (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Terry Chen, Malik Hsu, Tim Wawrzynczak. Hello Terry Chen, Malik Hsu, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62465 to look at the new patch set (#2). Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked ...................................................................... mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked Config GPP_B3 unlocked to make reboot works on primus. BUG=b:221488504 TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage test reboot 30 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62465/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Gerrit-Change-Number: 62465 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022