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Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
Would you mind basing this on CB:59548, where the structure is as it should be already? I'll push an update
File src/mainboard/clevo/tgl-u/bootblock.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/da18137b_fa8e3359
PS1, Line 16: if (onoff) {
: gpio_set(DGPU_RST_N, 0);
: mdelay(4);
: gpio_set(DGPU_PWR_EN, 1);
: mdelay(4);
: gpio_set(DGPU_RST_N, 1);
: } else {
: gpio_set(DGPU_RST_N, 0);
: mdelay(4);
: gpio_set(DGPU_PWR_EN, 0);
hmm, this looks like non-board-specific, generic code, that should be located in src/driver somewhere
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Change subject: treewide: Drop unused Kconfig symbols
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/moli/memory.c:
https://review.coreboot.org/c/coreboot/+/62478/comment/b9d2d047_08d5da9b
PS1, Line 13:
You will still need to return this config, e.g.
```
const struct mb_cfg *variant_memory_params(void)
{
return &ddr4_mem_config;
}
```
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Change subject: acpi/acpi: drop weak cpu_get_lapic_addr implementation
......................................................................
Patch Set 1: Code-Review+2
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Name of user not set #1003801 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62349 )
Change subject: soc/amd/common/fsp/fsp_validate.c: print warning instead of error
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62349/comment/627118c9_a300a05e
PS2, Line 10: warning instead of an error.
> Why? Is that for CI testing, or is it expected to have such FSP binaries?
The FSP spec, IIRC, doesn't require valid image revision info. The older AMD FSPs attempt to provide one but fail and instead put in '1'. I fixed that since but older FSP binaries will still be around for a while.
Patchset:
PS1:
> > No Signed-off-by line in commit message
done
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Change subject: arch/riscv: Fix build with binutils 2.38
......................................................................
Abandoned
old binutils do not support 'zicsr' 'zifencei' extensions. Please see 61767
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61767
to look at the new patch set (#11).
Change subject: crossgcc: Upgrade binutils from 2.37 to 2.38
......................................................................
crossgcc: Upgrade binutils from 2.37 to 2.38
mips patch is not needed anymore as mips is removed from coreboot.
Change-Id: I94a11e52be878b13eae9f00f7d6dc1ab2053693e
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/arch/riscv/Makefile.inc
M util/crossgcc/buildgcc
D util/crossgcc/patches/binutils-2.37_mips-gold.patch
R util/crossgcc/patches/binutils-2.38_as-ipxe.patch
R util/crossgcc/patches/binutils-2.38_no-bfd-doc.patch
R util/crossgcc/patches/binutils-2.38_no-makeinfo.patch
D util/crossgcc/sum/binutils-2.37.tar.xz.cksum
A util/crossgcc/sum/binutils-2.38.tar.xz.cksum
8 files changed, 51 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/61767/11
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62502 )
Change subject: acpi/acpi: drop weak cpu_get_lapic_addr implementation
......................................................................
acpi/acpi: drop weak cpu_get_lapic_addr implementation
All SoCs/chipsets that select ARCH_X86 will end up using the
implementation in cpu/x86/lapic/lapic.c, so to avoid confusion, drop the
unused weak implementation that returns a different value.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iffcd8c80260f9a7d81dda41a0ad08bffc7620c33
---
M src/acpi/acpi.c
1 file changed, 0 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/62502/1
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 4e2b8df..f7545b2 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -224,15 +224,6 @@
return lapic_nmi->length;
}
-__weak uintptr_t cpu_get_lapic_addr(void)
-{
- /*
- * If an architecture does not support LAPIC, this weak implementation returns LAPIC
- * addr as 0.
- */
- return 0;
-}
-
void acpi_create_madt(acpi_madt_t *madt)
{
acpi_header_t *header = &(madt->header);
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Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak,
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Change subject: mb/google/glados: Drop TPM PIRQ
......................................................................
mb/google/glados: Drop TPM PIRQ
The Infineon TPM 1.2 used on glados boards doesn't use a PIRQ;
Linux only works with 'tpm.tis_interrupts=0" and Windows fails to
init the TPM citing a lack of available resources. With the PIRQ
removed, both Linux and Windows are happy / the TPM is available
for use.
Test: build/boot Linux 5.16.x and Windows 11 on google/chell
Change-Id: I544695505291bbebe062df636cc8ddd139c08c2b
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/glados/variants/asuka/include/variant/gpio.h
M src/mainboard/google/glados/variants/caroline/include/variant/gpio.h
M src/mainboard/google/glados/variants/cave/include/variant/gpio.h
M src/mainboard/google/glados/variants/chell/include/variant/gpio.h
M src/mainboard/google/glados/variants/glados/include/variant/gpio.h
M src/mainboard/google/glados/variants/lars/include/variant/gpio.h
M src/mainboard/google/glados/variants/sentry/include/variant/gpio.h
8 files changed, 7 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/62444/2
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