coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/glados: Drop TPM PIRQ
by Matt DeVillier (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62444 ) Change subject: mb/google/glados: Drop TPM PIRQ ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hmmm, no saying I know better, but this would leave the GPIO […] you're right, I should set the GPIOs to NC as well. I've done that here and the TPM still functions as expected (per cbmem and linux tpm_* commands) -- To view, visit https://review.coreboot.org/c/coreboot/+/62444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I544695505291bbebe062df636cc8ddd139c08c2b Gerrit-Change-Number: 62444 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 18:00:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Raul Rangel (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Robert Zieba, Martin Roth, Paul Menzel, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Patch Set 27: (5 comments) File src/soc/amd/cezanne/fch.c: https://review.coreboot.org/c/coreboot/+/61259/comment/b8e3edc0_47834fe0 PS27, Line 159: clk_req Can we call this `dxio_clk_req` so I don't have to trace where it came from? https://review.coreboot.org/c/coreboot/+/61259/comment/94115267_d9c64540 PS27, Line 162: clk_req is only 4 bits Nice catch https://review.coreboot.org/c/coreboot/+/61259/comment/e75f2434_a2de8b05 PS27, Line 176: - Is `clk_req == CLK_DISABLE` not valid? Do we want that throwing an assert? https://review.coreboot.org/c/coreboot/+/61259/comment/2627cc7e_a1acb508 PS27, Line 178: assert Just FYI, assert only dies if compiled with FATAL_ASSERT. Otherwise we just keep going... https://review.coreboot.org/c/coreboot/+/61259/comment/1063b917_d98ed4a5 PS27, Line 196: if (fw_config_probe_dev(pci_device, &probe)) { : /* : * fw_config probes don't touch the SoC gpp_clk_config. : * So there's only a mismatch if the device was disabled : * by something other than a probe. : */ : printk(BIOS_WARNING, : "GPP clk req mismatch: %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n", : dxio_desc->device_number, : dxio_desc->function_number, gpp_req_index, i); : } else { Part of me feels like we should just remove this whole chunk. -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 27 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 17:50:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Felix Held (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Robert Zieba, Raul Rangel, Martin Roth, Paul Menzel, Rob Barnes, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Patch Set 27: (1 comment) Patchset: PS27: have you tested the case of a device being enabled, but not physically present? so what would happen if for example the wifi card of a chromebook gets removed; will things behave as expected in that case? -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 27 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 17:40:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie: Always enable developer mode
by Felix Held (Code Review) 01 Mar '22

01 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62341 ) Change subject: mb/amd/chausie: Always enable developer mode ...................................................................... mb/amd/chausie: Always enable developer mode Chausie doesn't have recovery mode buttons so it's impossible to manually enter recovery mode to enable developer mode. This means we need to force developer mode. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/chausie/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig index e3e079a..88c4d0a 100644 --- a/src/mainboard/amd/chausie/Kconfig +++ b/src/mainboard/amd/chausie/Kconfig @@ -76,6 +76,8 @@ config CHROMEOS # Use default libpayload config select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + # We don't have recovery buttons, so we can't manually enable devmode. + select GBB_FLAG_FORCE_DEV_SWITCH_ON if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE -- To view, visit https://review.coreboot.org/c/coreboot/+/62341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Gerrit-Change-Number: 62341 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/chausie: Always enable developer mode
by Felix Held (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62341 ) Change subject: mb/amd/chausie: Always enable developer mode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Gerrit-Change-Number: 62341 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 17:29:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer
by Raul Rangel (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62501 ) Change subject: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer ...................................................................... soc/amd/common/vboot: Verify location of CBMEMC transfer buffer Since we want to read the non-x86 CBMEMC from SMM we need to be stricter on where we read from. This change forces the verstage binary and x86 code to agree on the CBMEMC transfer buffer location and size. BUG=b:221231786 TEST=Boot guybrush and verify verstage transfer buffer still ends up in cbmem Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f --- M src/soc/amd/common/vboot/transfer_buffer.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/62501/1 diff --git a/src/soc/amd/common/vboot/transfer_buffer.c b/src/soc/amd/common/vboot/transfer_buffer.c index 63b4f8e..e08847e 100644 --- a/src/soc/amd/common/vboot/transfer_buffer.c +++ b/src/soc/amd/common/vboot/transfer_buffer.c @@ -10,6 +10,8 @@ #include <timestamp.h> #include <2struct.h> +DECLARE_REGION(cbmemc_transfer) + int transfer_buffer_valid(const struct transfer_info_struct *ptr) { if (ptr->magic_val == TRANSFER_MAGIC_VAL && ptr->struct_bytes == sizeof(*ptr)) @@ -85,6 +87,13 @@ cbmemc = (void *)((uintptr_t)info + info->console_offset); + /* Verify the cbmemc transfer buffer is where we expect it to be. */ + if ((void *)_cbmemc_transfer != (void *)cbmemc) + return; + + if (REGION_SIZE(cbmemc_transfer) != cbmemc_size) + return; + /* We need to manually initialize cbmemc so we can fill the new buffer. cbmemc_init() * will also be called later in console_hw_init(), but it will be a no-op. */ cbmemc_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/62501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Gerrit-Change-Number: 62501 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
by Raul Rangel (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello Jason Glenesk, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62402 to look at the new patch set (#2). Change subject: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem ...................................................................... soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem Now that SMM can write to CBMEM we can simply replay the transfer buffer cbmem console to move it into the main cbmem console. replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols. Since the SMM rmodule get linked with a different linker script than bootblock/romstage it doesn't have access to these symbols. In order to pass these symbols into SMM, we parse the bootblock.map file and generate an early_ram.ld script. This script is then used when linking SMM. I replay the buffer in `smm_soc_early_init` because this call happens before `console_init()`. `console_init()` prints the SMM header and we want to append the verstage contents before printing the header to avoid confusion. BUG=b:221231786 TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when doing `cbmem -c`. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c --- M src/soc/amd/cezanne/smihandler.c M src/soc/amd/common/vboot/Makefile.inc A src/soc/amd/common/vboot/early_ram_symbols.awk 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/62402/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Gerrit-Change-Number: 62402 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resume
by Raul Rangel (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62347 to look at the new patch set (#2). Change subject: soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resume ...................................................................... soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resume We need to save the transfer buffer so we can transfer the cbmem console and timestamps into x86 DRAM. BUG=b:221231786 TEST=Boot guybrush and verify S0i3 resume works. Also dumped the transfer buffer from the OS and verified the console contents got transferred. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b --- M src/soc/amd/common/psp_verstage/psp_verstage.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/62347/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b Gerrit-Change-Number: 62347 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Add weak SoC and mainboard init and exit methods
by Raul Rangel (Code Review) 01 Mar '22

01 Mar '22

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62500 ) Change subject: cpu/x86/smm: Add weak SoC and mainboard init and exit methods ...................................................................... cpu/x86/smm: Add weak SoC and mainboard init and exit methods This change provides hooks for the SoC and mainboard so they can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 --- M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/62500/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 49ea016..b8cb95d 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -162,6 +162,9 @@ init_cbmemc_region(); + smm_soc_early_init(); + smm_mainboard_early_init(); + console_init(); printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); @@ -191,6 +194,9 @@ die("SMM Handler caused a stack overflow\n"); } + smm_mainboard_exit(); + smm_soc_exit(); + smi_release_lock(); /* De-assert SMI# signal to allow another SMI */ @@ -211,3 +217,8 @@ int __weak mainboard_smi_apmc(u8 data) { return 0; } void __weak mainboard_smi_sleep(u8 slp_typ) {} void __weak mainboard_smi_finalize(void) {} + +void __weak smm_soc_early_init(void) {} +void __weak smm_mainboard_early_init(void) {} +void __weak smm_mainboard_exit(void) {} +void __weak smm_soc_exit(void) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 28d95e1..625f808 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -51,6 +51,11 @@ void mainboard_smi_sleep(u8 slp_typ); void mainboard_smi_finalize(void); +void smm_soc_early_init(void); +void smm_mainboard_early_init(void); +void smm_mainboard_exit(void); +void smm_soc_exit(void); + /* This is the SMM handler. */ extern unsigned char _binary_smm_start[]; extern unsigned char _binary_smm_end[]; -- To view, visit https://review.coreboot.org/c/coreboot/+/62500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Gerrit-Change-Number: 62500 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
by Raul Rangel (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Tim Wawrzynczak, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62355 ) Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI ...................................................................... Patch Set 2: (1 comment) File src/include/cpu/x86/smm.h: https://review.coreboot.org/c/coreboot/+/62355/comment/3d60a9ac_f9c35fa5 PS1, Line 64: void *cbmemc; : u32 cbmemc_size; > nit: care to swap those around? That makes the struct entries aligned on 64bit mode. […] SGTM. I wonder if we should convert `smbase` and `gnvs_ptr` to `void *` in a follow up. -- To view, visit https://review.coreboot.org/c/coreboot/+/62355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Gerrit-Change-Number: 62355 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 17:20:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit March 2022