coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/zork: fix SMMSTORE size, alignment in default FMAP
by Raul Rangel (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Matt DeVillier, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62443 ) Change subject: mb/google/zork: fix SMMSTORE size, alignment in default FMAP ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62443/comment/1fd87318_7c92a04c PS1, Line 9: 64k Where is this documented? https://review.coreboot.org/c/coreboot/+/62443/comment/4c71634c_e8038adb PS1, Line 12: asserts Which asserts? File src/mainboard/google/zork/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/62443/comment/0b1c36fb_1bb79497 PS1, Line 15: RW_ELOG(PRESERVE) 4K : RW_SHARED 16K { : SHARED_DATA 8K : VBLOCK_DEV 8K : } : RW_VPD(PRESERVE) 8K : RW_NVRAM(PRESERVE) 20K This is going to invalidate all this data. Can you maybe add some padding before SMMSTORE? -- To view, visit https://review.coreboot.org/c/coreboot/+/62443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8 Gerrit-Change-Number: 62443 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 15:45:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Marina Michelle has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/62290 ) Change subject: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/62290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Gerrit-Change-Number: 62290 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MH...
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Yu-Ping Wu, Felix Held. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Paul Menzel, Yu-Ping Wu, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62530 to review the following change. Change subject: Revert "soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test" ...................................................................... Revert "soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test" This reverts commit c89f252608d87d7db7731fdd9c80b4bed0e33b9b. Reason for revert: <INSERT REASONING HERE> No good Change-Id: Icb83c806d9da6be346d7b099847a79a63bf9202d --- M src/soc/mediatek/mt8186/include/soc/rtc.h M src/soc/mediatek/mt8186/rtc.c 2 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/62530/1 diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h index a3fb7a0..3a0c7cd 100644 --- a/src/soc/mediatek/mt8186/include/soc/rtc.h +++ b/src/soc/mediatek/mt8186/include/soc/rtc.h @@ -143,7 +143,6 @@ PMIC_RG_DCXO_CW00 = 0x0788, PMIC_RG_DCXO_CW00_CLR = 0x078C, PMIC_RG_DCXO_CW02 = 0x0790, - PMIC_RG_DCXO_CW03 = 0x0794, PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW09 = 0x079E, PMIC_RG_DCXO_CW11 = 0x07A2, diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 2f78be8..528f42b 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -13,8 +13,6 @@ #include <soc/pmic_wrap.h> #include <timer.h> -#define MT8186_RTC_DXCO_CAPID 0xC0 - /* Initialize RTC setting of using DCXO clock */ static bool rtc_enable_dcxo(void) { @@ -233,16 +231,6 @@ rtc_write(PMIC_RG_DCXO_CW23, 0x0052); } -static void rtc_set_capid(u16 capid) -{ - u16 read_capid; - - rtc_write(PMIC_RG_DCXO_CW03, 0xFF00 | capid); - - rtc_read(PMIC_RG_DCXO_CW03, &read_capid); - rtc_info("read back capid: %#x\n", read_capid & 0xFF); -} - /* Check RTC Initialization */ int rtc_init(int recover) { @@ -349,8 +337,6 @@ rtc_write(PMIC_RG_DCXO_CW09, 0x408F); mdelay(5); - rtc_set_capid(MT8186_RTC_DXCO_CAPID); - mt6366_dcxo_disable_unused(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb83c806d9da6be346d7b099847a79a63bf9202d Gerrit-Change-Number: 62530 Gerrit-PatchSet: 1 Gerrit-Owner: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
by build bot (Jenkins) (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Felix Singer, Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support ...................................................................... Patch Set 3: (1 comment) File src/mainboard/clevo/tgl-u/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142927): https://review.coreboot.org/c/coreboot/+/62498/comment/4eca9a49_8814d27a PS3, Line 14: static void dgpu_power_enable(int onoff) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 15:37:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/docker/coreboot-jenkins-node: Alphabetize installed tools
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Marina Michelle has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/62446 ) Change subject: util/docker/coreboot-jenkins-node: Alphabetize installed tools ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/62446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48 Gerrit-Change-Number: 62446 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "util/docker/coreboot-jenkins-node: Alphabetize installed tools"
by Marina Michelle (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Felix Singer, Martin Roth, Felix Held. Hello Felix Singer, build bot (Jenkins), Martin Roth, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62529 to review the following change. Change subject: Revert "util/docker/coreboot-jenkins-node: Alphabetize installed tools" ...................................................................... Revert "util/docker/coreboot-jenkins-node: Alphabetize installed tools" This reverts commit 1fcf78cc8eff90881d5d03e38408d584f66a5035. Reason for revert: <INSERT REASONING HERE> Not running Change-Id: I8922f82d5d7ed193fa94ddf81e0e699c86a3eb78 --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 10 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/62529/1 diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 526487e..2926163 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -25,16 +25,12 @@ RUN apt-get -y update && \ apt-get -y install \ - default-jre-headless \ - liblua5.3-dev \ - linkchecker \ - lua5.3 \ - meson \ - ninja-build \ - openssh-server \ - parallel \ - sdcc \ - && apt-get clean + parallel \ + meson ninja-build \ + sdcc \ + linkchecker \ + lua5.3 liblua5.3-dev default-jre-headless openssh-server && \ + apt-get clean # Because of the way that the variables are being replaced, docker's 'COPY' # command does not work @@ -67,17 +63,10 @@ COPY --from=zephyr-sdk /opt/zephyr-sdk /opt/zephyr-sdk RUN apt-get update && \ - apt-get install -y \ - python3-pip \ - pykwalify \ - python3-yaml \ - python3-pyelftools \ - python3-jsonschema \ - python3-colorama \ - python3-pyrsistent \ - python3-setuptools \ - swig \ - && apt-get clean + apt-get install -y python3-pip pykwalify python3-yaml \ + python3-pyelftools python3-jsonschema python3-colorama \ + python3-pyrsistent python3-setuptools swig && \ + apt-get clean RUN mkdir /tmp/b && cd /tmp/b && \ git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git dtc && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/62529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8922f82d5d7ed193fa94ddf81e0e699c86a3eb78 Gerrit-Change-Number: 62529 Gerrit-PatchSet: 1 Gerrit-Owner: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
by build bot (Jenkins) (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 ) Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 ...................................................................... Patch Set 3: Verified+1 (1 comment) File src/drivers/gfx/nvidia/optimus/optimus.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142925): https://review.coreboot.org/c/coreboot/+/62496/comment/5a42bc7a_4728d2a5 PS3, Line 261: const struct opregion rp_pci_config = OPREGION("PXCS", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS | (parent->path.pci.devfn << 12), 0x1000); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 Gerrit-Change-Number: 62496 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 15:26:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
by Michał Kopeć (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Felix Singer, Michał Żygowski. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support ...................................................................... Patch Set 3: (7 comments) File src/mainboard/clevo/tgl-u/Kconfig: https://review.coreboot.org/c/coreboot/+/62498/comment/2005846a_214e9e1b PS1, Line 6: BOARD_CLEVO_TGL_U_COMMON > Move this to the top please Done https://review.coreboot.org/c/coreboot/+/62498/comment/89b7895e_f8c24bfb PS1, Line 43: config MAINBOARD_FAMILY : string : default "Not Applicable" # Match stock firmware > Remove Done File src/mainboard/clevo/tgl-u/Kconfig.name: https://review.coreboot.org/c/coreboot/+/62498/comment/f0fad29e_676720f9 PS1, Line 5: select BOARD_CLEVO_NV4X_BASE > We don't do selects in this file, only in Kconfig. See clevo/cml-u/Kconfig. hmm, but that's exactly how it's done in clevo/cml-u/Kconfig{,.name}, or am I missing something here? File src/mainboard/clevo/tgl-u/mainboard.c: PS1: > Rename this file to ramstage. […] Done File src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62498/comment/61bc3dd8_8af4844c PS1, Line 3: gpio.c > Use early_gpio. […] Done File src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c: https://review.coreboot.org/c/coreboot/+/62498/comment/c72f54b4_7009efea PS1, Line 242: static const struct pad_config early_gpio_table[] = { : PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ : PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ : PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP), /* DGPU_RST#_PCH */ : PAD_CFG_TERM_GPO(GPP_U5, 0, NONE, DEEP), /* DGPU_PWR_EN */ : }; > Please use gpio_early.c, to align with the other Clevos. Done https://review.coreboot.org/c/coreboot/+/62498/comment/1c290b49_051c7881 PS1, Line 255: const struct pad_config *variant_early_gpio_table(size_t *num) : { : *num = ARRAY_SIZE(early_gpio_table); : return early_gpio_table; : } > I meant clevo/cml-u/variants/l140cu/gpio_early.c, sorry. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 15:18:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62540 ) Change subject: soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl ...................................................................... soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl After the patch that moved the generation of the PPKG object to Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65 --- M src/mainboard/amd/gardenia/dsdt.asl M src/mainboard/amd/padmelon/dsdt.asl M src/mainboard/google/kahlee/dsdt.asl R src/soc/amd/stoneyridge/acpi/pnot.asl 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/62540/1 diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 6c275a0..3759384 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -24,8 +24,8 @@ /* PCI IRQ mapping for the Southbridge */ #include <pcie.asl> - /* Describe the processor tree (\_SB) */ - #include <cpu.asl> + /* Power state notification */ + #include <pnot.asl> /* Contains the supported sleep states for this chipset */ #include <soc/amd/common/acpi/sleepstates.asl> diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 026acf4..6104597 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -22,8 +22,8 @@ /* PCI IRQ mapping for the Southbridge */ #include <pcie.asl> - /* Describe the processor tree (\_SB) */ - #include <cpu.asl> + /* Power state notification */ + #include <pnot.asl> /* Contains the supported sleep states for this chipset */ #include <soc/amd/common/acpi/sleepstates.asl> diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 4820306..be4033b 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -24,8 +24,8 @@ /* PCI IRQ mapping for the Southbridge */ #include <pcie.asl> - /* Describe the processor tree (\_SB) */ - #include <cpu.asl> + /* Power state notification */ + #include <pnot.asl> /* Contains the supported sleep states for this chipset */ #include <soc/amd/common/acpi/sleepstates.asl> diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/pnot.asl similarity index 100% rename from src/soc/amd/stoneyridge/acpi/cpu.asl rename to src/soc/amd/stoneyridge/acpi/pnot.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/62540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65 Gerrit-Change-Number: 62540 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62539 ) Change subject: soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries ...................................................................... soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Stoneyridge with the other AMD SoCs. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=None, but equivalent change on Picasso was verified to not break anything on Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611 --- M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/acpi/cpu.asl 2 files changed, 1 insertion(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/62539/1 diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 4c3b625..0a67088 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -151,7 +151,5 @@ acpigen_pop_len(); } - acpigen_write_scope("\\"); - acpigen_write_name_integer("PCNT", cores); - acpigen_pop_len(); + acpigen_write_processor_package("PPKG", 0, cores); } diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 24b81a1..818bcdb 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -4,42 +4,3 @@ Method (PNOT) { } - -/* - * Processor Object - */ -/* These devices are created at runtime */ -External (\PCNT, IntObj) -External (\_SB.P000, DeviceObj) -External (\_SB.P001, DeviceObj) -External (\_SB.P002, DeviceObj) -External (\_SB.P003, DeviceObj) -External (\_SB.P004, DeviceObj) -External (\_SB.P005, DeviceObj) -External (\_SB.P006, DeviceObj) -External (\_SB.P007, DeviceObj) - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (\PCNT >= 4) { - Return (Package () - { - \_SB.P000, - \_SB.P001, - \_SB.P002, - \_SB.P003 - }) - } ElseIf (\PCNT>= 2) { - Return (Package () - { - \_SB.P000, - \_SB.P001 - }) - } Else { - Return (Package () - { - \_SB.P000 - }) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/62539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611 Gerrit-Change-Number: 62539 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2022