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Change subject: mb/google/glados: Drop TPM PIRQ
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
> there is not one reported. Per src/drivers/pc80/tpm/tis. […]
Ack
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Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
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Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62374/comment/821ef32f_fcb86e99
PS6, Line 7: mb/google/brask/variants/moli :
> please put the colon `:` next to `moli`, e.g. […]
Done
https://review.coreboot.org/c/coreboot/+/62374/comment/76228f4b_f1705564
PS6, Line 7: set psys_imax_ma for moli
> Maybe: […]
Done
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Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
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Patch Set 9: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62374/comment/544c6a0d_1fcb3087
PS2, Line 9: set psys_imax_ma to 11000 mA for moli
> I'm pretty sure this is the rating of the power supply (AC adapter)
Approximately, yes.
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Change subject: mb/google/brask/variants/moli: init overridetree for moli
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Patch Set 8:
(1 comment)
Patchset:
PS8:
+Subrata and Eric, any good suggestions for the panel face to put the ports on? this is a box/base design, not a laptop
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Change subject: soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl
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Change subject: mb/google/brask/variants/moli: set up gpio
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Patch Set 9: Code-Review+2
(2 comments)
File src/mainboard/google/brya/variants/moli/gpio.c:
https://review.coreboot.org/c/coreboot/+/62314/comment/71b1a306_b4b342a6
PS7, Line 26: PAD_CFG_GPI(GPP_B23, NONE, DEEP),
> Why is this an input? It's the same signal as the baseboard, PCHHOT# which we are not currently usin […]
Done
https://review.coreboot.org/c/coreboot/+/62314/comment/6a131278_d6d3813b
PS7, Line 48: /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
: PAD_CFG_GPO(GPP_E6, 1, DEEP),
> I think the baseboard setting is OK here?
Done
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Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
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Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/moli/memory.c:
https://review.coreboot.org/c/coreboot/+/62478/comment/8c1f3d0b_c2c74403
PS4, Line 9: .ddr_config = {
Seems like you will need some other settings here, too
e.g.
```
.type = MEM_TYPE_DDR4,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = {50, 20, 25, 25, 25},
},
.ect = 1, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
```
to match brask
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