coreboot-gerrit March 2022

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Change in coreboot[master]: soc/amd/common/vboot: Split transfer buffer methods into separate file
by Joey Madafferi (Code Review) 02 Mar '22

02 Mar '22

Joey Madafferi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62348 ) Change subject: soc/amd/common/vboot: Split transfer buffer methods into separate file ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: Yes love it -- To view, visit https://review.coreboot.org/c/coreboot/+/62348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Gerrit-Change-Number: 62348 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 22:43:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer
by Joey Madafferi (Code Review) 02 Mar '22

02 Mar '22

Joey Madafferi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62501 ) Change subject: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Gerrit-Change-Number: 62501 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 22:41:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: bsd/cb_err: Add error code for UEFI variable store
by Joey Madafferi (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Patrick Rudolph. Joey Madafferi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61960 ) Change subject: bsd/cb_err: Add error code for UEFI variable store ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Run✅ -- To view, visit https://review.coreboot.org/c/coreboot/+/61960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90 Gerrit-Change-Number: 61960 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph Gerrit-Comment-Date: Wed, 02 Mar 2022 22:37:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/northbridge,root_complex: add comment about PCI BARs
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62547 ) Change subject: soc/amd/*/northbridge,root_complex: add comment about PCI BARs ...................................................................... soc/amd/*/northbridge,root_complex: add comment about PCI BARs Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/62547/1 diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index dabfa78..9cb668e 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -114,6 +114,9 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* 0x0 - 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index a3a3d4b..d5fd10d 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -114,6 +114,9 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* 0x0 - 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index 2a3ed6f..ae1b3b9 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -116,6 +116,9 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* 0x0 - 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 0384e00..85ef19e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -60,6 +60,9 @@ unsigned int idx = 0; struct resource *res; + /* The northbridge has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in -- To view, visit https://review.coreboot.org/c/coreboot/+/62547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Gerrit-Change-Number: 62547 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62546 ) Change subject: soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index ...................................................................... soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index In the northbridge's and root complex' read_resources function, the GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8061364879d772469882fc060f92676de6f600a9 --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/62546/1 diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index e29b4e0..dabfa78 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -168,7 +168,7 @@ } /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic = new_resource(dev, idx++); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 076588e..a3a3d4b 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -166,7 +166,7 @@ } /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic = new_resource(dev, idx++); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index fc49f4f..2a3ed6f 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -170,7 +170,7 @@ } /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic = new_resource(dev, idx++); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 0a80648..0384e00 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -68,7 +68,7 @@ mmconf_resource(dev, idx++); /* NB IOAPIC2 resource */ - res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res = new_resource(dev, idx++); /* IOAPIC2 */ res->base = IO_APIC2_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -- To view, visit https://review.coreboot.org/c/coreboot/+/62546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8061364879d772469882fc060f92676de6f600a9 Gerrit-Change-Number: 62546 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/northbridge,root_complex: simplify mmconf_resource index
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62545 ) Change subject: soc/amd/*/northbridge,root_complex: simplify mmconf_resource index ...................................................................... soc/amd/*/northbridge,root_complex: simplify mmconf_resource index In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62545/1 diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index dde59d4..e29b4e0 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -138,7 +138,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB); - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); if (!hob) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4ea8bc2..076588e 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -136,7 +136,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB); - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); if (!hob) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index e73c30e..fc49f4f 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -140,7 +140,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB); - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); if (!hob) { printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 04472dc..0a80648 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -57,6 +57,7 @@ static void read_resources(struct device *dev) { + unsigned int idx = 0; struct resource *res; /* @@ -64,7 +65,7 @@ * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); /* NB IOAPIC2 resource */ res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Gerrit-Change-Number: 62545 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: timestamps: Rename timestamps to make names more consistent
by Joey Madafferi (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Raul Rangel, Jakub Czapiga, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Lee Leahy, Marshall Dawson, Fred Reitberger, Yu-Ping Wu, Felix Held. Joey Madafferi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62019 ) Change subject: timestamps: Rename timestamps to make names more consistent ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: £run✅ -- To view, visit https://review.coreboot.org/c/coreboot/+/62019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Gerrit-Change-Number: 62019 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Mar 2022 22:20:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Robert Zieba (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Raul Rangel, Martin L Roth, Paul Menzel, Rob Barnes, Karthik Ramasubramanian. Robert Zieba has removed Jason Glenesk from this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Removed reviewer Jason Glenesk. -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 29 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Robert Zieba (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Raul Rangel, Martin L Roth, Paul Menzel, Rob Barnes, Karthik Ramasubramanian. Robert Zieba has removed Fred Reitberger from this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Removed reviewer Fred Reitberger. -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 29 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Robert Zieba (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Raul Rangel, Martin L Roth, Paul Menzel, Rob Barnes, Karthik Ramasubramanian. Robert Zieba has removed Marshall Dawson from this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Removed reviewer Marshall Dawson. -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 29 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: deleteReviewer

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coreboot-gerrit March 2022