coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
by Zoey Wu (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Zoey Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62478 ) Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/moli/memory.c: https://review.coreboot.org/c/coreboot/+/62478/comment/da4d4749_e8c03f51 PS4, Line 9: .ddr_config = { > Seems like you will need some other settings here, too […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d Gerrit-Change-Number: 62478 Gerrit-PatchSet: 5 Gerrit-Owner: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Mar 2022 00:27:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: cbmem_console: Drop loglevel markers from snapshot
by Julius Werner (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Raul Rangel, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62506 ) Change subject: libpayload: cbmem_console: Drop loglevel markers from snapshot ...................................................................... Patch Set 1: (3 comments) File payloads/libpayload/drivers/cbmem_console.c: https://review.coreboot.org/c/coreboot/+/62506/comment/611ba8a9_55bc67d6 PS1, Line 120: /* Slight memory corruption may occur between reboots and give us a few : unprintable characters like '\0'. Replace them with '?' on output. */ : for (cursor = 0; cursor < size; cursor++) : if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) : console_c[cursor] = '?'; > Are you suggesting a callback? Yes, including <commonlib/loglevel.h> directly in libpayload.h would be a problem. However, depthcharge is GPL so including <commonlib/loglevel.h> directly from the respective depthcharge file interpreting this should be fine. A problem is just that the commonlib integration (see CB:59697, CB:59916 and CB:60171) currently only covers commonlib/bsd... so if you wanted to do this you'd have to extend that to also cover commonlib/include directly (and that part should be gated by CONFIG_LP_GPL, which we are setting for Chrome OS). I'm fine with either option but I don't have the time to implement a more complicated solution here, so let me know if someone else wants to do that and I'll abandon this. https://review.coreboot.org/c/coreboot/+/62506/comment/a41258f6_ee303ce5 PS1, Line 85: Due to stupid : licensing restrictions > Why can you add a BSD version in libpayload? You are the copyright holder. […] Yeah, I've thought about several different ways to do this before deciding not to bother. BIOS_LOG_IS_MARKER is my copyright, but it depends on BIOS_LOG_PREFIX_MAX_LEVEL (also mine) which depends on BIOS_LOG_SPEW (not mine) -- so basically I'd have to relicense the whole file. The BIOS_LOG_xxx integers alone could probably be copied without exceeding the copyright threshold, but for the documentation comments on them that's not so clear (which were written by some guy in 2015 who as far as I know isn't currently active in the community). So I basically started rewriting all those documentation comments in my own words trying to say the same thing without copying any phrase directly, and then I realized that I have better things I could waste my time on. https://review.coreboot.org/c/coreboot/+/62506/comment/b91508f6_79bf9ab8 PS1, Line 90: memory corruption may occur between reboots > Side note: I just learned that the kernel ramoops has an ECC function to correct errors like this. […] I don't really think this is a big enough problem in practice to be worth that effort, tbh. That would probably be a bunch of extra code you have to link into and run in every coreboot stage. When I've seen corruption in practice, it's usually just a few sprinkled single characters that don't really hurt readability. This code is just here because when one of those few characters flipped to '\0', you don't want it to cut off the rest of the log. (Also, this pretty much only used to happen for cold resets... and it seems on our more recent devices DRAM usually just can't survive a cold reset at all instead. I'm not quite sure where that came from, I think it may have to do with LPDDR3 being more fragile to this than the older technologies or something.) -- To view, visit https://review.coreboot.org/c/coreboot/+/62506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9e5d464508320cf43ea572d62896d38c2a128d Gerrit-Change-Number: 62506 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 00:19:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
by Karthik Ramasubramanian (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62402 ) Change subject: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Gerrit-Change-Number: 62402 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Mar 2022 00:18:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
by Raul Rangel (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62402 to look at the new patch set (#5). Change subject: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem ...................................................................... soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem Now that SMM can write to CBMEM we can simply replay the transfer buffer cbmem console to move it into the main cbmem console. replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols. Since the SMM rmodule get linked with a different linker script than bootblock/romstage it doesn't have access to these symbols. In order to pass these symbols into SMM, we parse the bootblock.map file and generate an early_ram.ld script. This script is then used when linking SMM. I replay the buffer in `smm_soc_early_init` because this call happens before `console_init()`. `console_init()` prints the SMM header and we want to append the verstage contents before printing the header to avoid confusion. BUG=b:221231786 TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when doing `cbmem -c`. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c --- M src/soc/amd/cezanne/smihandler.c M src/soc/amd/common/vboot/Makefile.inc A src/soc/amd/common/vboot/early_ram_symbols.awk 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/62402/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Gerrit-Change-Number: 62402 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
by Raul Rangel (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62402 to look at the new patch set (#4). Change subject: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem ...................................................................... soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem Now that SMM can write to CBMEM we can simply replay the transfer buffer cbmem console to move it into the main cbmem console. replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols. Since the SMM rmodule get linked with a different linker script than bootblock/romstage it doesn't have access to these symbols. In order to pass these symbols into SMM, we parse the bootblock.map file and generate an early_ram.ld script. This script is then used when linking SMM. I replay the buffer in `smm_soc_early_init` because this call happens before `console_init()`. `console_init()` prints the SMM header and we want to append the verstage contents before printing the header to avoid confusion. BUG=b:221231786 TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when doing `cbmem -c`. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c --- M src/soc/amd/cezanne/smihandler.c M src/soc/amd/common/vboot/Makefile.inc A src/soc/amd/common/vboot/early_ram_symbols.awk 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/62402/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Gerrit-Change-Number: 62402 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/glados: Restore ChromeEC tablet mode switch for caroline, cave
by Matt DeVillier (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Tim Wawrzynczak. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62447 ) Change subject: mb/google/glados: Restore ChromeEC tablet mode switch for caroline, cave ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62447/comment/c616ecc2_9dffb75c PS1, Line 9: Commit 017b5c45 [ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config] > nit: wrap lines at 72 characters. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d Gerrit-Change-Number: 62447 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Mar 2022 23:43:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
by Raul Rangel (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Tim Wawrzynczak, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62355 ) Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62355/comment/f6e48472_3828a078 PS2, Line 24: and call that from smm_module_handler. > Maybe a nicer way would be to define an smm_get_cbmemc_buffer(void *buffer_out, size_t *size_out) fu […] Done File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/62355/comment/b732157c_0d1a931f PS2, Line 17: size_t cbmemc_size; > Since these are global symbols, please namespace them a bit better (e.g. […] Ack File src/lib/cbmem_console.c: https://review.coreboot.org/c/coreboot/+/62355/comment/7f208a28_253738d7 PS2, Line 90: extern size_t cbmemc_size; > These should probably go in some SMM-specific header and then be included here. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Gerrit-Change-Number: 62355 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 23:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/smm: Add weak SoC and mainboard init and exit methods
by Raul Rangel (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Martin Roth, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Martin Roth, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62500 to look at the new patch set (#2). Change subject: cpu/x86/smm: Add weak SoC and mainboard init and exit methods ...................................................................... cpu/x86/smm: Add weak SoC and mainboard init and exit methods This change provides hooks for the SoC and mainboard so they can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 --- M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/62500/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Gerrit-Change-Number: 62500 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
by Raul Rangel (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Tim Wawrzynczak, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Hello Arthur Heymans, build bot (Jenkins), Nico Huber, Martin Roth, Tim Wawrzynczak, Julius Werner, Angel Pons, Rob Barnes, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62355 to look at the new patch set (#3). Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI ...................................................................... cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI This change will allow the SMI handler to write to the cbmem console buffer. Normally SMIs can only be debugged using some kind of serial port (UART). By storing the SMI logs into cbmem we can debug SMIs using `cbmem -1`. Now that these logs are available to the OS we could also verify there were no errors in the SMI handler. Since SMM can write to all of DRAM, we can't trust any pointers provided by cbmem after the OS has booted. For this reason we store the cbmem console pointer as part of the SMM runtime parameters. The cbmem console is implemented as a circular buffer so it will never write outside of this area. BUG=b:221231786 TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are visible when running `cbmem -1`. Perform a suspend/resume cycle and verify new SMI events are written to the cbmem console log. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/include/console/cbmem_console.h M src/include/cpu/x86/smm.h M src/lib/Makefile.inc M src/lib/cbmem_console.c 6 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62355/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Gerrit-Change-Number: 62355 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork: fix SMMSTORE size, alignment in default FMAP
by Raul Rangel (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Matt DeVillier, Arthur Heymans, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62443 ) Change subject: mb/google/zork: fix SMMSTORE size, alignment in default FMAP ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > it's enabled by default when Tianocore is the selected payload :) Oh, that's why I've never seen it :) -- To view, visit https://review.coreboot.org/c/coreboot/+/62443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8 Gerrit-Change-Number: 62443 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 23:33:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022