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Change subject: soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg
......................................................................
soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B
recovery. Both bootloader can be put in the fw.cfg. The amdfwtool
decides which booloader is dropped in the directory.
Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/fw.cfg
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/56937/67
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I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Add ISH header support for A/B recovery layout
......................................................................
amdfwtool: Add ISH header support for A/B recovery layout
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
0x4A -> ISH B -> PSP L2 B -> BIOS L2 B
Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/Makefile
M util/amdfwtool/Makefile.inc
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
4 files changed, 64 insertions(+), 12 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Check the length of matching string before accessing
......................................................................
amdfwtool: Check the length of matching string before accessing
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.
Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/data_parse.c
1 file changed, 22 insertions(+), 10 deletions(-)
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
---
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
3 files changed, 529 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/7
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Peter Ou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62466 )
Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/brya/variants/kano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62466/comment/c5d78ec7_8e3f3ff0
PS3, Line 134: 20000
> Lowering PL1 max power value will impact the overall system performance.
our thermal design target is 18~20w, we still concern the thermal event when PL1 is over the TDP so we adjust the power limit.
https://review.coreboot.org/c/coreboot/+/62466/comment/f69c8c73_556bf104
PS3, Line 141: 43000
> Normally, we keep max and min power value the same for PL2. […]
please David help to change the PL2_Mix/Min to 43W.
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Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62542 )
Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
Patch Set 1:
(1 comment)
File spd/lp5/memory_parts.json:
https://review.coreboot.org/c/coreboot/+/62542/comment/40595c7c_a918c653
PS1, Line 54: "name": "MT62F2G32D8DR-031 WT:B",
> This part operates in Byte mode, where two dies combine together to form a standard x16 channel. […]
I think this is correct for ADL at least. The set 0 SPD matches advisory #616599 slide 14 column 3 (x32 315balls, 8Gb die, ODP 2R 8GB).
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Attention is currently required from: Hung-Te Lin, Ryan Chuang.
Hello Ryan Chuang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62550
to review the following change.
Change subject: soc/mediatek/mt8195: Update header version from 1.8.1 to 1.9.1
......................................................................
soc/mediatek/mt8195: Update header version from 1.8.1 to 1.9.1
Move some structures to common folder (CB:61293), so we need to update
header version.
BUG=none
TEST=dram calibration pass
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: Id82cbef9cb10dba71489ea96f67c329de9aadc49
---
M src/soc/mediatek/mt8195/include/soc/dramc_param.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/62550/1
diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
index 11efbe1..38055ea 100644
--- a/src/soc/mediatek/mt8195/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
@@ -13,7 +13,7 @@
#include <soc/dramc_param_common.h>
#include <soc/dramc_soc.h>
-#define DRAMC_PARAM_HEADER_VERSION 8
+#define DRAMC_PARAM_HEADER_VERSION 9
struct sdram_params {
u32 rank_num;
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Hello Ryan Chuang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62549
to review the following change.
Change subject: soc/mediatek/mt8192: Update header version from 1.7.1 to 1.8.1
......................................................................
soc/mediatek/mt8192: Update header version from 1.7.1 to 1.8.1
Move some structures to common folder (CB:61293), so we need to update
header version for this.
BUG=none
TEST=dram calibration pass
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: I8cf12f4967af116eaef88c1f688567f1da9fa6e4
---
M src/soc/mediatek/mt8192/include/soc/dramc_param.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/62549/1
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
index a5357c9..c4f1293 100644
--- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
@@ -13,7 +13,7 @@
#include <soc/dramc_param_common.h>
#include <soc/dramc_soc.h>
-#define DRAMC_PARAM_HEADER_VERSION 7
+#define DRAMC_PARAM_HEADER_VERSION 8
struct sdram_params {
u32 rank_num;
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