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Change subject: libpayload: cbmem_console: Drop loglevel markers from snapshot
......................................................................
Patch Set 1:
(1 comment)
File payloads/libpayload/drivers/cbmem_console.c:
https://review.coreboot.org/c/coreboot/+/62506/comment/3e343db7_6421739b
PS1, Line 120: /* Slight memory corruption may occur between reboots and give us a few
: unprintable characters like '\0'. Replace them with '?' on output. */
: for (cursor = 0; cursor < size; cursor++)
: if (!isprint(console_c[cursor]) && !isspace(console_c[cursor]))
: console_c[cursor] = '?';
> I'm fine with either option but I don't have the time to implement a more complicated solution here, so let me know if someone else wants to do that and I'll abandon this.
I don't have time to make highlighting texts in the log viewer either. However, I quickly created CL:3500781 to drop the markers in depthcharge. For that to take effect we just need to remove the code block here.
The solution I mentioned in b/221909874 could be postponed until someone really have the time to do it (maybe an intern project?). Does the plan sound good to you?
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Change subject: amdfwtool: Check the length of matching string before accessing
......................................................................
Abandoned
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Nikolai Vyssotski, Fred Reitberger, Felix Held,
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Change subject: amdfwtool: Change the some FW's level for A/B recovery
......................................................................
amdfwtool: Change the some FW's level for A/B recovery
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.
The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.
Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/fw.cfg
M util/amdfwtool/amdfwtool.c
2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/62329/12
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Change subject: soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg
......................................................................
soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B
recovery. Both bootloader can be put in the fw.cfg. The amdfwtool
decides which booloader is dropped in the directory.
Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/fw.cfg
1 file changed, 1 insertion(+), 0 deletions(-)
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Change subject: amdfwtool: Add ISH header support for A/B recovery layout
......................................................................
amdfwtool: Add ISH header support for A/B recovery layout
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
0x4A -> ISH B -> PSP L2 B -> BIOS L2 B
Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/Makefile
M util/amdfwtool/Makefile.inc
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
4 files changed, 64 insertions(+), 12 deletions(-)
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Change subject: amdfwtool: Check the length of matching string before accessing
......................................................................
amdfwtool: Check the length of matching string before accessing
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.
Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/data_parse.c
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
---
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
3 files changed, 529 insertions(+), 0 deletions(-)
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Peter Ou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62466 )
Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/brya/variants/kano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62466/comment/c5d78ec7_8e3f3ff0
PS3, Line 134: 20000
> Lowering PL1 max power value will impact the overall system performance.
our thermal design target is 18~20w, we still concern the thermal event when PL1 is over the TDP so we adjust the power limit.
https://review.coreboot.org/c/coreboot/+/62466/comment/f69c8c73_556bf104
PS3, Line 141: 43000
> Normally, we keep max and min power value the same for PL2. […]
please David help to change the PL2_Mix/Min to 43W.
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