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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by build bot (Jenkins) (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62553 ) Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/kinox/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142983): https://review.coreboot.org/c/coreboot/+/62553/comment/2b8589f2_4f30e54e PS1, Line 247: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Mar 2022 06:00:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by Dtrain Hsu (Code Review) 03 Mar '22

03 Mar '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62553 ) Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... mb/google/brya/var/kinox: update overridetree 1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. 3. Update 15W SOC default PL2/PL4(39W/100W). 4. Update fan table. BUG=b:218786363, b:212183045, b:213417026, b:221180425 TEST=emerge-brya coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc --- M src/mainboard/google/brya/variants/kinox/Makefile.inc M src/mainboard/google/brya/variants/kinox/overridetree.cb A src/mainboard/google/brya/variants/kinox/ramstage.c 3 files changed, 410 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62553/1 diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc index 58c4d79..681c764 100644 --- a/src/mainboard/google/brya/variants/kinox/Makefile.inc +++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc @@ -2,3 +2,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 4f2c04a..9b16aeb 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -1,6 +1,345 @@ chip soc/intel/alderlake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + }" - device domain 0 on - end + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Rear USB Type A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB HUB + + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # BTB + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 + + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(80, 97), + TEMP_PCT(65, 93), + TEMP_PCT(58, 86), + TEMP_PCT(50, 80), + TEMP_PCT(45, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [4] = { + .target = DPTF_TEMP_SENSOR_4, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie_rp6 on + # Enable PCIe-to-eMMC bridge PCIE 6 using clk 1 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 BH799BBLN + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" + register "enable_aspm_l1_2" = "1" + device pci 00.0 on end + end + end # RTL8111K Ethernet NIC + device ref pcie_rp8 off end + device ref pcie_rp9 off end + + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref tbt_pcie_rp2 off end # Disable TCP Port 2 + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end + + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C0 + device ref gspi1 off end + + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Hub"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Hub"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb3_port4 on end + end + end + end + end + end end diff --git a/src/mainboard/google/brya/variants/kinox/ramstage.c b/src/mainboard/google/brya/variants/kinox/ramstage.c new file mode 100644 index 0000000..9260a8c --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/ramstage.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in brask, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 13.52A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 13.52A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.47 = 15K / (15K + 16.9K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 13.52A = 202.8W + * For Type-C 20V, the Psys_pmax should be 20v x 13.52A = 270.4W + * For a barrel jack, the Psys_pmax should be 19.5v x 13.52A = 263.6W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 270.4W. Then IMVP9.1 can calculate the current system + * power = 270.4W * 5A / 13.52A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 13520, + .bj_volts_mv = 19500 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
by Karthik Ramasubramanian (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Nick Vaccaro. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62387 ) Change subject: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) ...................................................................... Patch Set 2: (1 comment) File util/spd_tools/src/spd_gen/lp5.go: https://review.coreboot.org/c/coreboot/+/62387/comment/c78b3cbd_3b0bc10f PS1, Line 587: if ok == false || tCKMinPs == 0 { : return LP5GetDefaultTCKMinPs(memAttribs) : } > I'm not sure if it makes sense to handle arbitrary speed grades since we've already validated the sp […] I defined the default speed to TCKMinPs mapping inside the earlier table. Speed validation ensures that the concerned speed is defined in that table. There is still a possibility that someone might forget to add the speedToTCKMinPs map for one or more SoC set. Under that scenario, I have updated the code to log a message and encode TCKMinPs as 0. Hope that addresses your concerns. Please re-open the comment if you are still not convinced. -- To view, visit https://review.coreboot.org/c/coreboot/+/62387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Gerrit-Change-Number: 62387 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 05:56:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: set up gpio
by Raihow Shi (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Zoey Wu, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62314 ) Change subject: mb/google/brask/variants/moli: set up gpio ...................................................................... Patch Set 9: (3 comments) File src/mainboard/google/brya/variants/moli/gpio.c: https://review.coreboot.org/c/coreboot/+/62314/comment/b1b45955_98744311 PS7, Line 26: PAD_CFG_GPI(GPP_B23, NONE, DEEP), > Why is this an input? It's the same signal as the baseboard, PCHHOT# which we are not currently usin […] done https://review.coreboot.org/c/coreboot/+/62314/comment/545cfbf0_cd57b9ae PS7, Line 48: /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ : PAD_CFG_GPO(GPP_E6, 1, DEEP), > I think the baseboard setting is OK here? done File src/mainboard/google/brya/variants/moli/ramstage.c: https://review.coreboot.org/c/coreboot/+/62314/comment/8ec65459_7ed68c48 PS1, Line 1: /* SPDX-License-Identifier: GPL-2.0-or-later */ > Adding this file should be a separate patch Hi Tim! I will add this file to a separate patch -- To view, visit https://review.coreboot.org/c/coreboot/+/62314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35 Gerrit-Change-Number: 62314 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Mar 2022 05:54:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
by Raihow Shi (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: YH Lin, Paul Menzel, Angel Pons, Zoey Wu, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62374 ) Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A ...................................................................... Patch Set 9: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62374/comment/37c71d20_f9d35153 PS2, Line 7: Moli: Review correctness of PSYS energy report > Please look through `git log --oneline` on how to write the prefix. done https://review.coreboot.org/c/coreboot/+/62374/comment/06cffbd7_5a79a822 PS2, Line 9: set psys_imax_ma to 11000 mA for moli > Why? Where is that number from? done Commit Message: https://review.coreboot.org/c/coreboot/+/62374/comment/a0a87be2_3469fe85 PS6, Line 7: set psys_imax_ma for moli > Maybe: […] done https://review.coreboot.org/c/coreboot/+/62374/comment/7be69f70_e98aaf56 PS6, Line 7: mb/google/brask/variants/moli : > please put the colon `:` next to `moli`, e.g. […] done -- To view, visit https://review.coreboot.org/c/coreboot/+/62374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99 Gerrit-Change-Number: 62374 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Mar 2022 05:53:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
by Karthik Ramasubramanian (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Karthik Ramasubramanian. Hello build bot (Jenkins), Tim Wawrzynczak, Reka Norman, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62387 to look at the new patch set (#2). Change subject: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) ...................................................................... util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 --- M spd/lp5/set-1/spd-1.hex M spd/lp5/set-1/spd-2.hex M spd/lp5/set-1/spd-3.hex M util/spd_tools/src/spd_gen/lp5.go 4 files changed, 42 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62387/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Gerrit-Change-Number: 62387 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
by Zoey Wu (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Zoey Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62478 ) Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/moli/memory.c: https://review.coreboot.org/c/coreboot/+/62478/comment/4fcc81ff_5f5ab20c PS4, Line 9: .ddr_config = { > Done Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d Gerrit-Change-Number: 62478 Gerrit-PatchSet: 5 Gerrit-Owner: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Mar 2022 05:26:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alder lake: Send EOP early in the boot sequence
by Maulik V Vaghela (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Subrata Banik, Sridhar Siricilla. Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62272 to look at the new patch set (#5). Change subject: soc/intel/alder lake: Send EOP early in the boot sequence ...................................................................... soc/intel/alder lake: Send EOP early in the boot sequence As part of boot time optimization, one of the culprit was CSE where response to End Of Post (EOP) command used to take ~60ms. Earlier patch was pushed to delay the EOP to reduce response time to ~5-7 ms. During this stage overall platform boot time was ~1.15 seconds. Once boot time was optimized to ~ 1 seconds, CSE EOP time again increased to ~80 ms since coreboot used to send EOP at the time where CSE was busy. This created some back and forth moving of sending EOP command function within coreboot sequence. Upon debugging using traces, it was found that coreboot used to send EOP late where CSE was busy loading other IP payload, so it might take more time to respond. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya board. Note that once SoC code sends EOP, coreboot common code won't send it again since common code already has check in case EOP is sent earlier. BUG=b:211085685 BRANCH=None TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62272/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
by EricR Lai (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: David Wu, Tim Wawrzynczak, Ren Kuo, Nick Vaccaro, Alan Huang, Peter Ou. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62466 ) Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c Gerrit-Change-Number: 62466 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 05:07:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
by Sumeet R Pawnikar (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: David Wu, Tim Wawrzynczak, Ren Kuo, Nick Vaccaro, Alan Huang, EricR Lai, Peter Ou. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62466 ) Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c Gerrit-Change-Number: 62466 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 04:51:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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