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Change subject: mb/google/brask/variants/moli: set up gpio
......................................................................
Patch Set 9:
(3 comments)
File src/mainboard/google/brya/variants/moli/gpio.c:
https://review.coreboot.org/c/coreboot/+/62314/comment/b1b45955_98744311
PS7, Line 26: PAD_CFG_GPI(GPP_B23, NONE, DEEP),
> Why is this an input? It's the same signal as the baseboard, PCHHOT# which we are not currently usin […]
done
https://review.coreboot.org/c/coreboot/+/62314/comment/545cfbf0_cd57b9ae
PS7, Line 48: /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
: PAD_CFG_GPO(GPP_E6, 1, DEEP),
> I think the baseboard setting is OK here?
done
File src/mainboard/google/brya/variants/moli/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62314/comment/8ec65459_7ed68c48
PS1, Line 1: /* SPDX-License-Identifier: GPL-2.0-or-later */
> Adding this file should be a separate patch
Hi Tim!
I will add this file to a separate patch
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Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
......................................................................
Patch Set 9:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62374/comment/37c71d20_f9d35153
PS2, Line 7: Moli: Review correctness of PSYS energy report
> Please look through `git log --oneline` on how to write the prefix.
done
https://review.coreboot.org/c/coreboot/+/62374/comment/06cffbd7_5a79a822
PS2, Line 9: set psys_imax_ma to 11000 mA for moli
> Why? Where is that number from?
done
Commit Message:
https://review.coreboot.org/c/coreboot/+/62374/comment/a0a87be2_3469fe85
PS6, Line 7: set psys_imax_ma for moli
> Maybe: […]
done
https://review.coreboot.org/c/coreboot/+/62374/comment/7be69f70_e98aaf56
PS6, Line 7: mb/google/brask/variants/moli :
> please put the colon `:` next to `moli`, e.g. […]
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Hello build bot (Jenkins), Tim Wawrzynczak, Reka Norman, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62387
to look at the new patch set (#2).
Change subject: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
......................................................................
util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle
time. Encode tCKMin as per the respective advisories.
BUG=None
TEST=Generate the SPD and ensure that tCKMin is encoded accordingly.
Minimum CAS Latency time is also impacted and is encoded accordingly.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26
---
M spd/lp5/set-1/spd-1.hex
M spd/lp5/set-1/spd-2.hex
M spd/lp5/set-1/spd-3.hex
M util/spd_tools/src/spd_gen/lp5.go
4 files changed, 42 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62387/2
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Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/moli/memory.c:
https://review.coreboot.org/c/coreboot/+/62478/comment/4fcc81ff_5f5ab20c
PS4, Line 9: .ddr_config = {
> Done
Done
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Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alder lake: Send EOP early in the boot sequence
......................................................................
soc/intel/alder lake: Send EOP early in the boot sequence
As part of boot time optimization, one of the culprit was CSE where
response to End Of Post (EOP) command used to take ~60ms. Earlier patch
was pushed to delay the EOP to reduce response time to ~5-7 ms. During
this stage overall platform boot time was ~1.15 seconds.
Once boot time was optimized to ~ 1 seconds, CSE EOP time again
increased to ~80 ms since coreboot used to send EOP at the time where
CSE was busy. This created some back and forth moving of sending EOP
command function within coreboot sequence.
Upon debugging using traces, it was found that coreboot used to send
EOP late where CSE was busy loading other IP payload, so it might take
more time to respond.
In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow where
FSP used to send EOP once silicon init is done and coreboot used to
rely on FSP to send this message.
Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time
reduces from ~60 ms to ~20 ms on Brya board.
Note that once SoC code sends EOP, coreboot common code won't send it
again since common code already has check in case EOP is sent earlier.
BUG=b:211085685
BRANCH=None
TEST=Tested on Brya system before and after the changes. Observed ~40ms
savings in boot time.
Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.c
2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62272/5
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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 4: Code-Review+2
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Usha P has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62513 )
Change subject: mb/google/brya/var/nivviks: Correct GPIO S7 config
......................................................................
Abandoned
Duplicate of CB:62511
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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/google/brya/variants/kano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62466/comment/409e12ca_43ee36ea
PS3, Line 141: 43000
> please David help to change the PL2_Mix/Min to 43W.
Done
File src/mainboard/google/brya/variants/kano/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62466/comment/80979da8_21d99deb
PS3, Line 10: 43000
> please David help to check the PL2_MIX and Min to 43W.
Done
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62466 )
Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> I feel it's fine.
Ack
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