coreboot-gerrit March 2022

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Change in coreboot[master]: payloads/tianocore: Add prompt for Boot Timeout
by Sean Rhodes (Code Review) 03 Mar '22

03 Mar '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62558 ) Change subject: payloads/tianocore: Add prompt for Boot Timeout ...................................................................... payloads/tianocore: Add prompt for Boot Timeout Add prompt to Boot Timeout so that it can be easily configured from a config file. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I62b8f0a9b5bc0796506b991199a457d6b34ae494 --- M payloads/external/tianocore/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/62558/1 diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 4194290..2cfe9ce 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -127,7 +127,7 @@ the default key of F2. config TIANOCORE_BOOT_TIMEOUT - int + int "Set the timeout for boot menu prompt" default 2 help The length of time in seconds for which the boot splash/menu prompt will be displayed. -- To view, visit https://review.coreboot.org/c/coreboot/+/62558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62b8f0a9b5bc0796506b991199a457d6b34ae494 Gerrit-Change-Number: 62558 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add ISH header support for A/B recovery layout
by Bao Zheng (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57747 to look at the new patch set (#58). Change subject: amdfwtool: Add ISH header support for A/B recovery layout ...................................................................... amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 4 files changed, 64 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/57747/58 -- To view, visit https://review.coreboot.org/c/coreboot/+/57747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Gerrit-Change-Number: 57747 Gerrit-PatchSet: 58 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00
by Ronak Kanabar (Code Review) 03 Mar '22

03 Mar '22

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62557 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00 ...................................................................... vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00 The headers added are generated as per FSP v3091_00 Previous FSP version was v2511_04 Changes include: - Update MemInfoHob.h BUG=b:222415800 BRANCH=None Change-Id: I260544e0502174ab141fa31ac78ede803b4f161e Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/62557/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h index 3722749..73a8d29 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -4,7 +4,7 @@ data hobs. @copyright - Copyright (c) 1999 - 2021, Intel Corporation. All rights reserved.<BR> + Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -18,6 +18,7 @@ #ifndef _MEM_INFO_HOB_H_ #define _MEM_INFO_HOB_H_ + #pragma pack (push, 1) extern EFI_GUID gSiMemoryS3DataGuid; @@ -256,7 +257,7 @@ SiMrcVersion Version; BOOLEAN EccSupport; UINT8 MemoryProfile; - UINT8 IsDMBRunning; ///< Memory Trained with Dynamic Memory Boost (DMB) + UINT8 IsDMBRunning; ///< Deprecated. UINT32 TotalPhysicalMemorySize; UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. /// @@ -278,6 +279,10 @@ UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 UINT32 NumPopulatedChannels; ///< Total number of memory channels populated HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population + BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. } MEMORY_INFO_DATA_HOB; /** -- To view, visit https://review.coreboot.org/c/coreboot/+/62557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I260544e0502174ab141fa31ac78ede803b4f161e Gerrit-Change-Number: 62557 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: spd/lp5: Add new part MT62F2G32D8DR-031
by Karthik Ramasubramanian (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Reka Norman, Jon Murphy, Tim Wawrzynczak, Amanda Hwang, Ivy Jian. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62542 ) Change subject: spd/lp5: Add new part MT62F2G32D8DR-031 ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Can you please rebase on top of CB:62387 File spd/lp5/memory_parts.json: https://review.coreboot.org/c/coreboot/+/62542/comment/4bc0a975_08778cb7 PS1, Line 54: "name": "MT62F2G32D8DR-031 WT:B", > I think this is correct for ADL at least. […] Ack. IIUC, there are 2 ways to handle this memory part 1) 4 channels of x8bits(Byte 6 - 0xF9, Byte 12 - 0x9) 2) Through byte mode, combine x8 bits from 2 dies into x16 bits. Then there will be 2 channels(Byte 6 - 0xF5, Byte 12 - 0x49) Let us go with option 1 for now. As per the reference SPDs shared by AMD, they advice option 2. I will double check with AMD and update if needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/62542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Gerrit-Change-Number: 62542 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 07:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Update DRAM population
by Teddy Shih (Code Review) 03 Mar '22

03 Mar '22

Teddy Shih has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/62556 ) Change subject: mb/google/dedede: Update DRAM population ...................................................................... mb/google/dedede: Update DRAM population In order to configure DRAM with half population for EVT all SKUs in Beadrix project with built-in 4 memory IC of Channel 0 and channel 1 (total 8 GB), we desolder 2 memory IC of Channel 1 (4 GB) according to mainboard schematic. We set half populated to 1 to indicate the only usage of 2 memory IC of Channel 0 (4 GB). The number of memory segments is passed to FSP for memory initialization. BUG=b:222232246 BRANCH=dedede TEST=Build and boot up beadrix built-in DRAM Channel 0 (4 GB) only. The number of memory information is passed to FSP. Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I8ec14c113ff7c355138e7b48640fb1766fb5958d --- M src/mainboard/google/dedede/variants/beadrix/memory.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62556/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec14c113ff7c355138e7b48640fb1766fb5958d Gerrit-Change-Number: 62556 Gerrit-PatchSet: 2 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Cha...
by Teddy Shih (Code Review) 03 Mar '22

03 Mar '22

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62556 ) Change subject: Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I8ec14c113ff7c355138e7b48640fb1766fb5958d ...................................................................... Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I8ec14c113ff7c355138e7b48640fb1766fb5958d --- M src/mainboard/google/dedede/variants/beadrix/memory.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62556/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory.c b/src/mainboard/google/dedede/variants/beadrix/memory.c index bfef45b..4b3b160 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory.c +++ b/src/mainboard/google/dedede/variants/beadrix/memory.c @@ -46,3 +46,13 @@ { return &board_memcfg_cfg; } + +int variant_memory_sku(void) +{ + return 0; +} + +bool variant_mem_is_half_populated(void) +{ + return 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec14c113ff7c355138e7b48640fb1766fb5958d Gerrit-Change-Number: 62556 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: cbmem_console: Drop loglevel markers from snapshot
by Yu-Ping Wu (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Raul Rangel, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62506 ) Change subject: libpayload: cbmem_console: Drop loglevel markers from snapshot ...................................................................... Patch Set 1: (1 comment) File payloads/libpayload/drivers/cbmem_console.c: https://review.coreboot.org/c/coreboot/+/62506/comment/dd57770b_ce15739a PS1, Line 120: /* Slight memory corruption may occur between reboots and give us a few : unprintable characters like '\0'. Replace them with '?' on output. */ : for (cursor = 0; cursor < size; cursor++) : if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) : console_c[cursor] = '?'; > For that to take effect we just need to remove the code block here. Correction. We still need to replace '\0' with '?' here. Otherwise the substring after '\0' would be discarded in payloads. -- To view, visit https://review.coreboot.org/c/coreboot/+/62506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9e5d464508320cf43ea572d62896d38c2a128d Gerrit-Change-Number: 62506 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Mar 2022 06:26:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli
by Subrata Banik (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 ) Change subject: mb/google/brask/variants/moli: init overridetree for moli ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > +Subrata and Eric, any good suggestions for the panel face to put the ports on? this is a box/base design, not a laptop I do suggest to use the same macro from here https://review.coreboot.org/c/coreboot/+/61801/11/src/include/acpi/acpi_pld… ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 1)) or ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 1)) etc. -- To view, visit https://review.coreboot.org/c/coreboot/+/62321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Gerrit-Change-Number: 62321 Gerrit-PatchSet: 8 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Mar 2022 06:14:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by Dtrain Hsu (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Tim Wawrzynczak. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62553 ) Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/kinox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62553/comment/d79a0851_9204958d PS1, Line 247: > trailing whitespace Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Mar 2022 06:08:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by Dtrain Hsu (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Dtrain Hsu, Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62553 to look at the new patch set (#2). Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... mb/google/brya/var/kinox: update overridetree 1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. 3. Update 15W SOC default PL2/PL4(39W/100W). 4. Update fan table. BUG=b:218786363, b:212183045, b:213417026, b:221180425 TEST=emerge-brya coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc --- M src/mainboard/google/brya/variants/kinox/Makefile.inc M src/mainboard/google/brya/variants/kinox/overridetree.cb A src/mainboard/google/brya/variants/kinox/ramstage.c 3 files changed, 409 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62553/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022