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Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
Patch Set 1:
(1 comment)
File spd/lp5/memory_parts.json:
https://review.coreboot.org/c/coreboot/+/62542/comment/5ae8bc65_ab894cca
PS1, Line 54: "name": "MT62F2G32D8DR-031 WT:B",
> This part operates in Byte mode, where two dies combine together to form a standard x16 channel. […]
I have uploaded datasheet to b\218606844#comment10 for your review, thanks.
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Hello build bot (Jenkins), Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61725
to look at the new patch set (#2).
Change subject: .mailmap: Add a .mailmap file for git
......................................................................
.mailmap: Add a .mailmap file for git
Git uses the .mailmap file to map author and committer names and email
addresses to canonical real names and email addresses.
Before adding this file, coreboot shows 1388 different author names and
email addresses because of typos, people changing email addresses, and
spelling their names differently.
After adding the file, the number of authors is down to 1016.
I tried to determine the best email address for each person by looking
at what they'd used most recently, but I can't promise that I correctly
picked the right address for everyone. Please take a look to make
sure that your email address and name is correct.
To enable .mailmap parsing globally, use:
$ git config --global log.mailmap true
To enable it just for a single log, run:
$ git log --use-mailmap
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I1f9b9bccc9322799234475a1cebf9808edd25693
---
A .mailmap
1 file changed, 425 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/61725/2
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Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62315 )
Change subject: mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreen
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/mainboard/google/dedede/variants/galtic/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62315/comment/eee91bf9_3c39abd8
PS3, Line 2: 39 40
> Are 2 bits sufficient? […]
yes, I have confirm with EC, no conflict with these bits
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Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/bb9b3812_5820aff5
PS3, Line 562: cbmemc = cbmem_entry_find(CBMEM_ID_CONSOLE);
nit: wrap in `if (CONFIG_CONSOLE_CBMEM)`?
File src/lib/cbmem_console.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/03641bc8_b1e5fbf6
PS3, Line 93: if (cbmemc != NULL && cbmemc_size > 0)
nit: init_console_ptr() already checks both of these
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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/kano/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62466/comment/dda2978c_6a360c86
PS3, Line 10: 43000
> Normally, we keep max and min value the same for PL2. […]
please David help to check the PL2_MIX and Min to 43W.
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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/kano/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62466/comment/3c4dffca_9b71f562
PS3, Line 10: 20000
> Added you to the bug.
This change base on thermal capacity, our thermal design target is 18~20w for U28 sku.
before change: PL1 is 28W, PL2 is 40w
1. Octane 2.0 score is 81991
2. speedometer2 score is 257
After change: PL1 to 20W, PL2 change 43w
1. Octane 2.0 score is 85148
2. speedometer2 score is 259
3. look like the performance is better when the PL1/PL2 be change in CB.
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Change subject: libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> LGTM except for the merge error
Oh I see, someone else did... hmmm. Guess something slipped through the spam filter? I think you'll need to upload patch set 1 again before we can proceed here.
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Change subject: libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
LGTM except for the merge error
File payloads/libpayload/bin/lpgcc:
https://review.coreboot.org/c/coreboot/+/62516/comment/2e7d7a38_6a70850a
PS2, Line 67: 61960: bsd/cb_err: Add error code for UEFI variable store | https://review.coreboot.org/c/coreboot/+/61960
?
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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3: -Code-Review
(1 comment)
Patchset:
PS3:
Wait for Sumeet's comment.
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Change subject: mb/google/brask/variants/moli: init overridetree for moli
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
For the box, depends on the HW design. Fornt and Back are adapt to the panel face.
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