coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/nissa: Add fmd file for nissa
by Kangheui Won (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62372 ) Change subject: mb/google/nissa: Add fmd file for nissa ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Gerrit-Change-Number: 62372 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 21:36:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer
by Raul Rangel (Code Review) 02 Mar '22

02 Mar '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62501 ) Change subject: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer ...................................................................... soc/amd/common/vboot: Verify location of CBMEMC transfer buffer Since we want to read the non-x86 CBMEMC from SMM we need to be stricter on where we read from. This change forces the verstage binary and x86 code to agree on the CBMEMC transfer buffer location and size. BUG=b:221231786 TEST=Boot guybrush and verify verstage transfer buffer still ends up in cbmem Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/vboot/transfer_buffer.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/vboot/transfer_buffer.c b/src/soc/amd/common/vboot/transfer_buffer.c index 63b4f8e..e08847e 100644 --- a/src/soc/amd/common/vboot/transfer_buffer.c +++ b/src/soc/amd/common/vboot/transfer_buffer.c @@ -10,6 +10,8 @@ #include <timestamp.h> #include <2struct.h> +DECLARE_REGION(cbmemc_transfer) + int transfer_buffer_valid(const struct transfer_info_struct *ptr) { if (ptr->magic_val == TRANSFER_MAGIC_VAL && ptr->struct_bytes == sizeof(*ptr)) @@ -85,6 +87,13 @@ cbmemc = (void *)((uintptr_t)info + info->console_offset); + /* Verify the cbmemc transfer buffer is where we expect it to be. */ + if ((void *)_cbmemc_transfer != (void *)cbmemc) + return; + + if (REGION_SIZE(cbmemc_transfer) != cbmemc_size) + return; + /* We need to manually initialize cbmemc so we can fill the new buffer. cbmemc_init() * will also be called later in console_hw_init(), but it will be a no-op. */ cbmemc_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/62501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Gerrit-Change-Number: 62501 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kinox: update gpio settings
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62364 ) Change subject: mb/google/brya/var/kinox: update gpio settings ...................................................................... mb/google/brya/var/kinox: update gpio settings Configure GPIOs according to schematics BUG=b:218786363 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62364 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/gpio.c 2 files changed, 161 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc new file mode 100644 index 0000000..58c4d79 --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/kinox/gpio.c b/src/mainboard/google/brya/variants/kinox/gpio.c new file mode 100644 index 0000000..0fbfee0 --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/gpio.c @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> TCP_DP1_HPD */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> TP153 */ + PAD_NC(GPP_B2, NONE), + + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* D18 : UART1_TXD ==> EMMC_PE_RST_L */ + PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), + /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ + + /* E4 : SATA_DEVSLP0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + /* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* H12 : I2C7_SDA ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520 Gerrit-Change-Number: 62364 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemc
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62401 ) Change subject: soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemc ...................................................................... soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemc We don't need to force the caller to look up and cast the transfer region. We can do it in the function. BUG=b:221231786 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/include/soc/psp_transfer.h M src/soc/amd/common/vboot/transfer_buffer.c M src/soc/amd/common/vboot/vboot_bootblock.c M src/soc/amd/picasso/include/soc/psp_transfer.h M src/soc/amd/sabrina/include/soc/psp_transfer.h 5 files changed, 10 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/psp_transfer.h b/src/soc/amd/cezanne/include/soc/psp_transfer.h index afa6a58..f81785e 100644 --- a/src/soc/amd/cezanne/include/soc/psp_transfer.h +++ b/src/soc/amd/cezanne/include/soc/psp_transfer.h @@ -54,7 +54,7 @@ /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); /* Replays the pre-x86 cbmem console into the x86 cbmem console */ -void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info); +void replay_transfer_buffer_cbmemc(void); /* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ void boot_with_psp_timestamp(uint64_t base_timestamp); diff --git a/src/soc/amd/common/vboot/transfer_buffer.c b/src/soc/amd/common/vboot/transfer_buffer.c index 06e564a..63b4f8e 100644 --- a/src/soc/amd/common/vboot/transfer_buffer.c +++ b/src/soc/amd/common/vboot/transfer_buffer.c @@ -61,12 +61,17 @@ } } -void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info) +void replay_transfer_buffer_cbmemc(void) { + const struct transfer_info_struct *info = (const struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; void *cbmemc; size_t cbmemc_size; + if (!transfer_buffer_valid(info)) + return; + if (info->console_offset < sizeof(*info)) return; diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 7264836..1375e98 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -14,7 +14,7 @@ if (!transfer_buffer_valid(info) || info->timestamp == 0) return; - replay_transfer_buffer_cbmemc(info); + replay_transfer_buffer_cbmemc(); /* * info->timestamp is PSP's timestamp (in microseconds) diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index 6b10ad2..5b51691 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -54,7 +54,7 @@ /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); /* Replays the pre-x86 cbmem console into the x86 cbmem console */ -void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info); +void replay_transfer_buffer_cbmemc(void); /* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ void boot_with_psp_timestamp(uint64_t base_timestamp); diff --git a/src/soc/amd/sabrina/include/soc/psp_transfer.h b/src/soc/amd/sabrina/include/soc/psp_transfer.h index 0fe204d..6e3faaf 100644 --- a/src/soc/amd/sabrina/include/soc/psp_transfer.h +++ b/src/soc/amd/sabrina/include/soc/psp_transfer.h @@ -56,7 +56,7 @@ /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); /* Replays the pre-x86 cbmem console into the x86 cbmem console */ -void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info); +void replay_transfer_buffer_cbmemc(void); /* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ void boot_with_psp_timestamp(uint64_t base_timestamp); -- To view, visit https://review.coreboot.org/c/coreboot/+/62401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Gerrit-Change-Number: 62401 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/vboot: Split transfer buffer methods into separate file
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62348 ) Change subject: soc/amd/common/vboot: Split transfer buffer methods into separate file ...................................................................... soc/amd/common/vboot: Split transfer buffer methods into separate file I want to reuse the transfer buffer methods in SMM, so I need to add them into their own file. I renamed `setup_cbmem_console` to `replay_transfer_buffer_cbmemc` so it has a more descriptive name. I also fixed the comment on `verify_psp_transfer_buf`. BUG=b:221231786 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/include/soc/psp_transfer.h M src/soc/amd/common/vboot/Makefile.inc A src/soc/amd/common/vboot/transfer_buffer.c M src/soc/amd/common/vboot/vboot_bootblock.c M src/soc/amd/picasso/include/soc/psp_transfer.h M src/soc/amd/sabrina/include/soc/psp_transfer.h 6 files changed, 102 insertions(+), 83 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/psp_transfer.h b/src/soc/amd/cezanne/include/soc/psp_transfer.h index 96cdae1..afa6a58 100644 --- a/src/soc/amd/cezanne/include/soc/psp_transfer.h +++ b/src/soc/amd/cezanne/include/soc/psp_transfer.h @@ -48,9 +48,13 @@ "TRANSFER_INFO_SIZE is incorrect"); /* Make sure the PSP transferred information over to x86 side. */ +int transfer_buffer_valid(const struct transfer_info_struct *ptr); +/* Verify vboot work buffer is valid in transfer buffer */ void verify_psp_transfer_buf(void); /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); +/* Replays the pre-x86 cbmem console into the x86 cbmem console */ +void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info); /* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ void boot_with_psp_timestamp(uint64_t base_timestamp); diff --git a/src/soc/amd/common/vboot/Makefile.inc b/src/soc/amd/common/vboot/Makefile.inc index 8a6f116..6938d16 100644 --- a/src/soc/amd/common/vboot/Makefile.inc +++ b/src/soc/amd/common/vboot/Makefile.inc @@ -6,3 +6,4 @@ endif bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += vboot_bootblock.c +bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += transfer_buffer.c diff --git a/src/soc/amd/common/vboot/transfer_buffer.c b/src/soc/amd/common/vboot/transfer_buffer.c new file mode 100644 index 0000000..06e564a --- /dev/null +++ b/src/soc/amd/common/vboot/transfer_buffer.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/reset.h> +#include <console/cbmem_console.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <security/vboot/vbnv.h> +#include <security/vboot/symbols.h> +#include <soc/psp_transfer.h> +#include <timestamp.h> +#include <2struct.h> + +int transfer_buffer_valid(const struct transfer_info_struct *ptr) +{ + if (ptr->magic_val == TRANSFER_MAGIC_VAL && ptr->struct_bytes == sizeof(*ptr)) + return 1; + else + return 0; +} + +void verify_psp_transfer_buf(void) +{ + if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { + cmos_write(0x00, CMOS_RECOVERY_BYTE); + return; + } + + /* + * If CMOS is valid and the system has already been rebooted once, but + * still returns here, instead of rebooting to verstage again, assume + * that the system is in a reboot loop and halt. + */ + if ((!vbnv_cmos_failed()) && cmos_read(CMOS_RECOVERY_BYTE) == + CMOS_RECOVERY_MAGIC_VAL) + die("Error: Reboot into recovery was unsuccessful. Halting."); + + printk(BIOS_ERR, "VBOOT workbuf not valid.\n"); + printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); + cmos_init(0); + cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); + warm_reset(); +} + +void show_psp_transfer_info(void) +{ + struct transfer_info_struct *info = (struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (transfer_buffer_valid(info)) { + if ((info->psp_info & PSP_INFO_VALID) == 0) { + printk(BIOS_INFO, "No PSP info found in transfer buffer.\n"); + return; + } + + printk(BIOS_INFO, "PSP boot mode: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_MODE ? + "Production" : "Development"); + printk(BIOS_INFO, "Silicon level: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_SILICON ? + "Production" : "Pre-Production"); + } +} + +void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info) +{ + + void *cbmemc; + size_t cbmemc_size; + + if (info->console_offset < sizeof(*info)) + return; + + if (info->timestamp_offset <= info->console_offset) + return; + + cbmemc_size = info->timestamp_offset - info->console_offset; + + if (info->console_offset + cbmemc_size > info->buffer_size) + return; + + cbmemc = (void *)((uintptr_t)info + info->console_offset); + + /* We need to manually initialize cbmemc so we can fill the new buffer. cbmemc_init() + * will also be called later in console_hw_init(), but it will be a no-op. */ + cbmemc_init(); + cbmemc_copy_in(cbmemc, cbmemc_size); +} diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index e3705d1..7264836 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -1,91 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/reset.h> #include <bootblock_common.h> -#include <console/cbmem_console.h> #include <console/console.h> -#include <pc80/mc146818rtc.h> -#include <security/vboot/vbnv.h> -#include <security/vboot/symbols.h> #include <soc/psp_transfer.h> +#include <symbols.h> #include <timestamp.h> -#include <2struct.h> - -static int transfer_buffer_valid(const struct transfer_info_struct *ptr) -{ - if (ptr->magic_val == TRANSFER_MAGIC_VAL && ptr->struct_bytes == sizeof(*ptr)) - return 1; - else - return 0; -} - -void verify_psp_transfer_buf(void) -{ - if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { - cmos_write(0x00, CMOS_RECOVERY_BYTE); - return; - } - - /* - * If CMOS is valid and the system has already been rebooted once, but - * still returns here, instead of rebooting to verstage again, assume - * that the system is in a reboot loop and halt. - */ - if ((!vbnv_cmos_failed()) && cmos_read(CMOS_RECOVERY_BYTE) == - CMOS_RECOVERY_MAGIC_VAL) - die("Error: Reboot into recovery was unsuccessful. Halting."); - - printk(BIOS_ERR, "VBOOT workbuf not valid.\n"); - printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); - cmos_init(0); - cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); - warm_reset(); -} - -void show_psp_transfer_info(void) -{ - struct transfer_info_struct *info = (struct transfer_info_struct *) - (void *)(uintptr_t)_transfer_buffer; - - if (transfer_buffer_valid(info)) { - if ((info->psp_info & PSP_INFO_VALID) == 0) { - printk(BIOS_INFO, "No PSP info found in transfer buffer.\n"); - return; - } - - printk(BIOS_INFO, "PSP boot mode: %s\n", - info->psp_info & PSP_INFO_PRODUCTION_MODE ? - "Production" : "Development"); - printk(BIOS_INFO, "Silicon level: %s\n", - info->psp_info & PSP_INFO_PRODUCTION_SILICON ? - "Production" : "Pre-Production"); - } -} - -static void setup_cbmem_console(const struct transfer_info_struct *info) -{ - - void *cbmemc; - size_t cbmemc_size; - - if (info->console_offset < sizeof(*info)) - return; - - if (info->timestamp_offset <= info->console_offset) - return; - - cbmemc_size = info->timestamp_offset - info->console_offset; - - if (info->console_offset + cbmemc_size > info->buffer_size) - return; - - cbmemc = (void *)((uintptr_t)info + info->console_offset); - - /* We need to manually initialize cbmemc so we can fill the new buffer. cbmemc_init() - * will also be called later in console_hw_init(), but it will be a no-op. */ - cbmemc_init(); - cbmemc_copy_in(cbmemc, cbmemc_size); -} void boot_with_psp_timestamp(uint64_t base_timestamp) { @@ -95,7 +14,7 @@ if (!transfer_buffer_valid(info) || info->timestamp == 0) return; - setup_cbmem_console(info); + replay_transfer_buffer_cbmemc(info); /* * info->timestamp is PSP's timestamp (in microseconds) diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index b5dffe7..6b10ad2 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -48,9 +48,13 @@ "TRANSFER_INFO_SIZE is incorrect"); /* Make sure the PSP transferred information over to x86 side. */ +int transfer_buffer_valid(const struct transfer_info_struct *ptr); +/* Verify vboot work buffer is valid in transfer buffer */ void verify_psp_transfer_buf(void); /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); +/* Replays the pre-x86 cbmem console into the x86 cbmem console */ +void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info); /* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ void boot_with_psp_timestamp(uint64_t base_timestamp); diff --git a/src/soc/amd/sabrina/include/soc/psp_transfer.h b/src/soc/amd/sabrina/include/soc/psp_transfer.h index 6055599..0fe204d 100644 --- a/src/soc/amd/sabrina/include/soc/psp_transfer.h +++ b/src/soc/amd/sabrina/include/soc/psp_transfer.h @@ -50,9 +50,13 @@ "TRANSFER_INFO_SIZE is incorrect"); /* Make sure the PSP transferred information over to x86 side. */ +int transfer_buffer_valid(const struct transfer_info_struct *ptr); +/* Verify vboot work buffer is valid in transfer buffer */ void verify_psp_transfer_buf(void); /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); +/* Replays the pre-x86 cbmem console into the x86 cbmem console */ +void replay_transfer_buffer_cbmemc(const struct transfer_info_struct *info); /* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ void boot_with_psp_timestamp(uint64_t base_timestamp); -- To view, visit https://review.coreboot.org/c/coreboot/+/62348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Gerrit-Change-Number: 62348 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer
by Karthik Ramasubramanian (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62501 ) Change subject: soc/amd/common/vboot: Verify location of CBMEMC transfer buffer ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Gerrit-Change-Number: 62501 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Mar 2022 21:10:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resume
by Felix Held (Code Review) 02 Mar '22

02 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62347 ) Change subject: soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resume ...................................................................... soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resume We need to save the transfer buffer so we can transfer the cbmem console and timestamps into x86 DRAM. BUG=b:221231786 TEST=Boot guybrush and verify S0i3 resume works. Also dumped the transfer buffer from the OS and verified the console contents got transferred. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/psp_verstage.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 05f0cda..9d0fb22 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -252,6 +252,11 @@ if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) { psp_verstage_s0i3_resume(); + post_code(POSTCODE_SAVE_BUFFERS); + retval = save_buffers(); + if (retval) + post_code(retval); + post_code(POSTCODE_UNMAP_FCH_DEVICES); unmap_fch_devices(); -- To view, visit https://review.coreboot.org/c/coreboot/+/62347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b Gerrit-Change-Number: 62347 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemc
by Karthik Ramasubramanian (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62401 ) Change subject: soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemc ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Gerrit-Change-Number: 62401 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Mar 2022 19:55:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/vboot: Split transfer buffer methods into separate file
by Karthik Ramasubramanian (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62348 ) Change subject: soc/amd/common/vboot: Split transfer buffer methods into separate file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Gerrit-Change-Number: 62348 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Mar 2022 19:52:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add compressed ME_RW blobs to ME_RW_A/B for ADL-N
by Tim Wawrzynczak (Code Review) 02 Mar '22

02 Mar '22

Attention is currently required from: Reka Norman, Jamie Ryu, Wonkyu Kim, Subrata Banik, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, Nick Vaccaro, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62358 ) Change subject: soc/intel/common: Add compressed ME_RW blobs to ME_RW_A/B for ADL-N ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62358/comment/c8fbaf8a_87fcc7a0 PS2, Line 88: ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) > Will this impact the ADL-P? If we don't touch the flashmap.md just reduce the size, should be fine. […] Agreed, would rather add a kconfig like ``` config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW bool default n depends on SOC_INTEL_CSE_LITE_SKU help..... ``` and then Nissa can select it. -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Mar 2022 19:44:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Balaji Manigandan <balaji.manigandan(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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