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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/kano/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62466/comment/982ebd2f_ff1ac947
PS3, Line 10: 20000
> Do you mean these new values are suggested by your thermal team for this platform ? […]
Added you to the bug.
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Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
......................................................................
Patch Set 3: -Code-Review
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62502 )
Change subject: acpi/acpi: drop weak cpu_get_lapic_addr implementation
......................................................................
acpi/acpi: drop weak cpu_get_lapic_addr implementation
All SoCs/chipsets that select ARCH_X86 will end up using the
implementation in cpu/x86/lapic/lapic.c, so to avoid confusion, drop the
unused weak implementation that returns a different value.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iffcd8c80260f9a7d81dda41a0ad08bffc7620c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62502
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/acpi/acpi.c
1 file changed, 0 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 4e2b8df..f7545b2 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -224,15 +224,6 @@
return lapic_nmi->length;
}
-__weak uintptr_t cpu_get_lapic_addr(void)
-{
- /*
- * If an architecture does not support LAPIC, this weak implementation returns LAPIC
- * addr as 0.
- */
- return 0;
-}
-
void acpi_create_madt(acpi_madt_t *madt)
{
acpi_header_t *header = &(madt->header);
--
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Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Lance Zhao
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62325 )
Change subject: mb/siemens/mc_ehl: Disable HS400 mode for eMMC
......................................................................
mb/siemens/mc_ehl: Disable HS400 mode for eMMC
In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.
Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 87b455f..d7c3e22 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -84,7 +84,7 @@
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "0"
- register "ScsEmmcHs400Enabled" = "1"
+ register "ScsEmmcHs400Enabled" = "0"
register "ScsEmmcDdr50Enabled" = "1"
register "SdCardPowerEnableActiveHigh" = "1"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 438419a..ffcf1da 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -69,7 +69,7 @@
register "PcieRpLtrDisable[6]" = "true"
# Storage (SDCARD/EMMC) related UPDs
- register "ScsEmmcHs400Enabled" = "1"
+ register "ScsEmmcHs400Enabled" = "0"
register "ScsEmmcDdr50Enabled" = "1"
register "SdCardPowerEnableActiveHigh" = "1"
--
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62451 )
Change subject: Documentation/mainboard: Add QEMU POWER9 to index site
......................................................................
Documentation/mainboard: Add QEMU POWER9 to index site
The QEMU POWER9 target is supported since coreboot version 4.15.
Documentation is available in the tree, but it's not referenced from
the mainboard index page. Fix that.
Change-Id: Ic3b98735840c146cb0bfb122df0e6f762c2beeca
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62451
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/mainboard/index.md
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Matt DeVillier: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 367cb1c..02383c9 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -52,6 +52,7 @@
- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
- [QEMU x86 Q35](emulation/qemu-q35.md)
- [QEMU x86 PC](emulation/qemu-i440fx.md)
+- [QEMU POWER9](emulation/qemu-power9.md)
## Facebook
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62450 )
Change subject: Documentation: Fix spelling of "QEMU"
......................................................................
Documentation: Fix spelling of "QEMU"
Fix spelling and use the one from their website qemu.org.
Change-Id: I36a88985ce3a7c59b732c1ca3198d86a591de6bd
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62450
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/mainboard/emulation/qemu-riscv.md
M Documentation/mainboard/index.md
2 files changed, 7 insertions(+), 7 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md
index 3aad816..ed2c6d5 100644
--- a/Documentation/mainboard/emulation/qemu-riscv.md
+++ b/Documentation/mainboard/emulation/qemu-riscv.md
@@ -1,8 +1,8 @@
-# Qemu RISC-V emulator
+# QEMU RISC-V emulator
-## Building coreboot and running it in Qemu
+## Building coreboot and running it in QEMU
- Configure coreboot and run `make` as usual
- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
- convert coreboot to an ELF that Qemu can load
+ convert coreboot to an ELF that QEMU can load
- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 5c41b91..367cb1c 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -48,10 +48,10 @@
The boards in this section are not real mainboards, but emulators.
- [Spike RISC-V emulator](emulation/spike-riscv.md)
-- [Qemu RISC-V emulator](emulation/qemu-riscv.md)
-- [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
-- [Qemu x86 Q35](emulation/qemu-q35.md)
-- [Qemu x86 PC](emulation/qemu-i440fx.md)
+- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
+- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
+- [QEMU x86 Q35](emulation/qemu-q35.md)
+- [QEMU x86 PC](emulation/qemu-i440fx.md)
## Facebook
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62449 )
Change subject: Documentation/mainboard: Add Supermicro X9SAE to index site
......................................................................
Documentation/mainboard: Add Supermicro X9SAE to index site
The Supermicro X9SAE target is supported since coreboot version 4.15.
Documentation is available in the tree, but it's not referenced from
the mainboard index page. Fix that.
Change-Id: I5d3d0b5b935f1a3ea353a3d9e39208db7c7895ef
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62449
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/mainboard/index.md
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 041a156..5c41b91 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -184,6 +184,7 @@
## Supermicro
+- [X9SAE](supermicro/x9sae.md)
- [X10SLM+-F](supermicro/x10slm-f.md)
- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62448 )
Change subject: Documentation: Fix spelling of "Supermicro"
......................................................................
Documentation: Fix spelling of "Supermicro"
Fix the spelling and use the one from their website supermicro.com
Change-Id: Id630d9d130082fb38f9151e0dfb6f6fbb5a2789d
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62448
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M Documentation/releases/coreboot-4.15-relnotes.md
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Matt DeVillier: Looks good to me, approved
diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md
index 087513e..75e01af 100644
--- a/Documentation/releases/coreboot-4.15-relnotes.md
+++ b/Documentation/releases/coreboot-4.15-relnotes.md
@@ -25,7 +25,7 @@
* Google nipperkin
* Lenovo w541
* Siemens mc_ehl
-* SuperMicro x9sae
+* Supermicro x9sae
* System76 addw1
* System76 addw2
* System76 bonw14
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Attention is currently required from: Henry Sun, Frank Chu, Shou-Chieh Hsu.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62315 )
Change subject: mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreen
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/dedede/variants/galtic/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62315/comment/6bdd2219_e4148656
PS3, Line 2: 39 40
Are 2 bits sufficient?
Did you ensure that there are no conflicts with these bits - both in AP and EC FW?
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62542 )
Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
Patch Set 1:
(1 comment)
File spd/lp5/memory_parts.json:
https://review.coreboot.org/c/coreboot/+/62542/comment/622ddce3_a3651af8
PS1, Line 54: "name": "MT62F2G32D8DR-031 WT:B",
This part operates in Byte mode, where two dies combine together to form a standard x16 channel. If so we may have to make some additional updates to the tool so that SPD is generated correctly. Can you please confirm with the part vendor?
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