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Hello build bot (Jenkins), Tim Wawrzynczak, Eric Lai,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
......................................................................
mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
Turn off the NFC power which is controlled by GPP_D3 to save power in
S0ix states. For an USB device, the S0ix hook is needed for the on/off
operations to take place.
BUG=b:202737385
BRANCH=firmware-brya-14505.B
TEST=measure the voltage of GPP_D3 in S0ix states
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3
---
M src/mainboard/google/brya/variants/brask/include/variant/gpio.h
M src/mainboard/google/brya/variants/brask/variant.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63191/3
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Change subject: soc/mediatek/early_init: Fix function return type
......................................................................
Patch Set 3: Code-Review+2
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Change subject: libpayload: Export PCIe config info from coreboot to libpayload
......................................................................
Patch Set 41:
(3 comments)
File payloads/libpayload/include/sysinfo.h:
https://review.coreboot.org/c/coreboot/+/57614/comment/8a94785e_ffed7e48
PS40, Line 148: uintptr_t pci_config_info;
Move this right below mem_chip_base?
File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h:
https://review.coreboot.org/c/coreboot/+/57614/comment/f40afaf9_081ead7a
PS40, Line 83: PCIE
PCI_INFO
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/57614/comment/5c29dec6_40196059
PS40, Line 100: cbmem_add
This should be done somewhere else in the pcie code, as the cbmem entry itself is unrelated to the coreboot table. Though I'm not sure whether we should move this to common code, or let each platform add the cbmem entry.
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Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform
......................................................................
Patch Set 38:
(3 comments)
File payloads/libpayload/drivers/pcie_mediatek.c:
https://review.coreboot.org/c/coreboot/+/56794/comment/d4cdfa91_64b7d90a
PS38, Line 22: pcie_base = base;
The base address can be stored in the coreboot table. We may need to wait for CB:57614 (or you can create a similar patch).
https://review.coreboot.org/c/coreboot/+/56794/comment/694e5d23_528e5b58
PS38, Line 29: & 0x7
Already included in the macro.
https://review.coreboot.org/c/coreboot/+/56794/comment/273f9af1_455ae28f
PS38, Line 29: & 0x1f
Already included in the macro.
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Change subject: Performance improvement by removing delays in cpucp init
......................................................................
Patch Set 2: Verified-1
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Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63190
to look at the new patch set (#3).
Change subject: soc/mediatek/early_init: Fix function return type
......................................................................
soc/mediatek/early_init: Fix function return type
Fix return type of early_init_get_elapsed_time_us() to comply with the
data type of return value.
Also replace memset() with struct initializer.
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Fixes: commit 41faa22 (soc/mediatek: Add early_init for passing data
across stages)
Change-Id: I7c361828362c2dfec91358ad8a420f5360243da0
---
M src/soc/mediatek/common/early_init.c
M src/soc/mediatek/common/include/soc/early_init.h
M src/soc/mediatek/common/pcie.c
3 files changed, 7 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63190/3
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Change subject: soc/qualcomm/common: verify size of memchipinfo structure
......................................................................
Patch Set 3:
(1 comment)
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/63026/comment/d34ef10c_cfd6cd49
PS1, Line 31: mem_chip_info_size(&memchip)
> Ravi, seriously, _please_ stop answering "Done" to things you didn't actually do! We're losing so mu […]
Sincere applogies julius.. and sorry for the inconvenience happened by me.
I thought this was older comment which is already address. that's the reason i have keep without seeing code changes.
I will not repeat these mistakes further.
I have addressed this comment.
Please let me know if any thing missing here.
Thanks.
Ravi
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