coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... Patch Set 39: (1 comment) File payloads/libpayload/drivers/pci_map_bus_ops.c: https://review.coreboot.org/c/coreboot/+/56789/comment/fbf0868c_ceb3ae19 PS35, Line 38: | > Is the address always aligned? I mean, should we write "+" here? The cfg_base should be 4K alignment, and the range of reg should be 0 ~ 4K for each device's config space. But it makes me wondering if we should remain the capability that some device may need 4Byte alignment access. For Mediatek chips, we will connect this address space (cfg_base) to AHB/AXI bus, so it's ok to access without 4Byte alignment. But if some device is connected to APB bus, it's only support 32bit access, so we should guarantee alignment and calculate the correct data here, just like the 'pci_generic_config_read32/write32' functions in Linux: https://elixir.bootlin.com/linux/latest/source/drivers/pci/access.c#L120 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 39 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 06:00:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Disable EN_SPKR on init
by Yu-hsuan Hsu (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Paul Menzel. Yu-hsuan Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63145 ) Change subject: mb/google/guybrush: Disable EN_SPKR on init ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63145/comment/b7fab051_b7b70d1f PS1, Line 10: using GPIO AMP codec in depthcharge. > It's for saving some power. You can refer to b/195748546 for the details. Thanks. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147 Gerrit-Change-Number: 63145 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 05:33:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
by Eric Lai (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Tim Wawrzynczak, Alan Huang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63191 ) Change subject: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Gerrit-Change-Number: 63191 Gerrit-PatchSet: 3 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 05:26:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Sridhar Siricilla (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Paul Menzel, Kane Chen. Hello build bot (Jenkins), Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63169 to look at the new patch set (#3). Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... soc/intel/common: Update CSE sub partition update The patch adds support in the CSE Sub partition update procedure to use GET_BOOT_PARTITION_INFO HECI command output to create the region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO HECI command provides CSE's RO and RW boot partition information. Existing code relies on FMD file to get the CSE's boot partition's (CSE RO and CSE RW) start and size details. This change make independent of FMD file declaration with respect to CSE RO and CSE RW. TEST=Build and verify the CSE RO and CSE RW region device information through code instrumentation. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 32 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63169/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Clear the whole byte of EFS_GEN
by Bao Zheng (Code Review) 30 Mar '22

30 Mar '22

Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63138 ) Change subject: amdfwtool: Clear the whole byte of EFS_GEN ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: validated on Majolica and Mandonlin(Picasso). -- To view, visit https://review.coreboot.org/c/coreboot/+/63138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Gerrit-Change-Number: 63138 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 04:33:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Sridhar Siricilla (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Paul Menzel, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63169 ) Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... Patch Set 2: (3 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/63169/comment/123aa102_6ad9a8d3 PS2, Line 3: #include <arch/cpu.h> > Unrelated. Ack https://review.coreboot.org/c/coreboot/+/63169/comment/76e6c2da_038b7096 PS2, Line 786: uint32_t size; : uint32_t start_offset; : uint32_t end_offset; > Why not `unsigned int`, `size_t` or `off_t`? Why not uint32_t? Any reason? https://review.coreboot.org/c/coreboot/+/63169/comment/b4b67e14_06152aca PS2, Line 804: region_name, (uint32_t)start_offset, (uint32_t)size); > Why are these casts needed? casts are not needed here. -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 04:25:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
by Sridhar Siricilla (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62843 ) Change subject: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/jasperlake/Kconfig: https://review.coreboot.org/c/coreboot/+/62843/comment/a2c97e79_5cbddc24 PS2, Line 71: SOC_INTEL_COMMON_BASECODE > should these also be qualified with […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Gerrit-Change-Number: 62843 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 03:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/devicetree: update PCI root ports
by 9elements QA (Code Review) 30 Mar '22

30 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63162 ) Change subject: mb/amd/chausie/devicetree: update PCI root ports ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/97910 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/97909 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/97908 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/97907 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/97906 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/97905 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/97904 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/97903 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/97902 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/97901 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/97900 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/97899 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I378c620abb6e52de680669b6edd228874153e399 Gerrit-Change-Number: 63162 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 03:04:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Yu-Ping Wu (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... Patch Set 39: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56789/comment/252048ea_1e213411 PS37, Line 7: libpayload/pci: Split PCI interfaces as common and chip related > Can we use "Add support for map bus"? It's more like we are adding map bus feature in this change. […] How about "Add support for bus mapping"? -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 39 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 02:56:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
by Alan Huang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Tim Wawrzynczak, Eric Lai. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63191 ) Change subject: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/brask/variant.c: https://review.coreboot.org/c/coreboot/+/63191/comment/c7e974dc_a2f7a8d8 PS2, Line 7: #include <soc/gpio.h> > We probably can remove this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Gerrit-Change-Number: 63191 Gerrit-PatchSet: 3 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 02:55:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022