coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
by Joey Peng (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Paul Menzel. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62954 ) Change subject: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62954/comment/f26400ef_505a4378 PS10, Line 9: fw > can you spell out […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Gerrit-Change-Number: 62954 Gerrit-PatchSet: 11 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 07:11:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
by Joey Peng (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Joey Peng, Paul Menzel. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62954 to look at the new patch set (#11). Change subject: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo ...................................................................... mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo Add thermal table settings for tarlo which shares the same firmware with taeko BUG=b:215033683 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 123 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62954/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/62954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Gerrit-Change-Number: 62954 Gerrit-PatchSet: 11 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/agah: Replace amp max98309 with max98360
by Tony Huang (Code Review) 30 Mar '22

30 Mar '22

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63196 ) Change subject: mb/google/brya/var/agah: Replace amp max98309 with max98360 ...................................................................... mb/google/brya/var/agah: Replace amp max98309 with max98360 Based on the latest schematic, replace amp max98390 with max98360. BUG=b:210970640 BRANCH=brya TEST=emerge-draco coreboot Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/agah/overridetree.cb 2 files changed, 9 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/63196/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index def0b31..6f3f2c3 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -4,7 +4,6 @@ bool "-> Agah" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9750 - select DRIVERS_I2C_MAX98390 select PCIEXP_SUPPORT_RESIZABLE_BARS select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 97fa990..a7286a8 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -127,28 +127,6 @@ register "property_list[0].integer" = "1" device i2c 1a on end end - chip drivers/i2c/max98390 - register "desc" = ""MAX98390 Speaker Amp 0"" - register "uid" = "0" - register "name" = ""MXW0"" - register "r0_calib_key" = ""dsm_calib_r0_0"" - register "temperature_calib_key" = ""dsm_calib_temp_0"" - register "dsm_param_file_name" = ""dsm_param_R"" - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" - device i2c 0x3a on end - end - chip drivers/i2c/max98390 - register "desc" = ""MAX98390 Speaker Amp 1"" - register "uid" = "1" - register "name" = ""MXW1"" - register "r0_calib_key" = ""dsm_calib_r0_1"" - register "temperature_calib_key" = ""dsm_calib_temp_1"" - register "dsm_param_file_name" = ""dsm_param_L"" - register "vmon_slot_no" = "1" - register "imon_slot_no" = "0" - device i2c 0x3b on end - end end #I2C0 device ref i2c1 on end # GPU device ref i2c2 on end # External GPU @@ -191,6 +169,15 @@ device generic 0 on end end end #PCIE8 SD card + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] -- To view, visit https://review.coreboot.org/c/coreboot/+/63196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc Gerrit-Change-Number: 63196 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/kinox: set GPP_D0 to NC
by Dtrain Hsu (Code Review) 30 Mar '22

30 Mar '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63195 ) Change subject: mb/google/brya/var/kinox: set GPP_D0 to NC ...................................................................... mb/google/brya/var/kinox: set GPP_D0 to NC Brask set GPP_D0 to GPO in CB:63090, but Kinox doesn't support fingerprint. This patch sets GPP_D0 to NC for matching schematic. BUG=b:214025396 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da --- M src/mainboard/google/brya/variants/kinox/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/63195/1 diff --git a/src/mainboard/google/brya/variants/kinox/gpio.c b/src/mainboard/google/brya/variants/kinox/gpio.c index ce55693..0accc52 100644 --- a/src/mainboard/google/brya/variants/kinox/gpio.c +++ b/src/mainboard/google/brya/variants/kinox/gpio.c @@ -24,6 +24,8 @@ /* B2 : VRALERT# ==> TP153 */ PAD_NC(GPP_B2, NONE), + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> NC */ PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), /* D2 : ISH_GP2 ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da Gerrit-Change-Number: 63195 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56794 ) Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... Patch Set 41: (2 comments) File payloads/libpayload/drivers/pcie_mediatek.c: https://review.coreboot.org/c/coreboot/+/56794/comment/7e004de9_419826e4 PS38, Line 29: & 0x7 > Already included in the macro. Done https://review.coreboot.org/c/coreboot/+/56794/comment/b7af4af5_2691f549 PS38, Line 29: & 0x1f > Already included in the macro. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 41 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 06:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/agah: Add GL9750 SD card reader support
by Tony Huang (Code Review) 30 Mar '22

30 Mar '22

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63194 ) Change subject: mb/google/brya/var/agah: Add GL9750 SD card reader support ...................................................................... mb/google/brya/var/agah: Add GL9750 SD card reader support BUG=b:210970640 TEST=emerge-draco coreboot Change-Id: I881c2c1ad7b0d10b7ae38fcd9814f757cf56feb5 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63194/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b3917d2..def0b31 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -3,6 +3,7 @@ config BOARD_GOOGLE_AGAH bool "-> Agah" select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_MAX98390 select PCIEXP_SUPPORT_RESIZABLE_BARS select RT8168_GEN_ACPI_POWER_RESOURCE -- To view, visit https://review.coreboot.org/c/coreboot/+/63194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I881c2c1ad7b0d10b7ae38fcd9814f757cf56feb5 Gerrit-Change-Number: 63194 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 40: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56789/comment/250471b6_b7912e68 PS37, Line 7: libpayload/pci: Split PCI interfaces as common and chip related > How about "Add support for bus mapping"? Done File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/56e496e7_e9bfe3c1 PS36, Line 405: PCI_COMMON > The config name should remain "PCI" in my opinion. Done https://review.coreboot.org/c/coreboot/+/56789/comment/eab728c5_2fb9f138 PS36, Line 411: select PCI_COMMON : default n > If one of PCI_MAP_BUS and PCI_IO_OPS must be set, then we don't need this extra config. We can use […] In that case, PCI_IO_OPS should be set to "default n", I'm not sure if this can work properly on x86 platform. https://review.coreboot.org/c/coreboot/+/56789/comment/e210f515_b8e0a916 PS36, Line 414: PCI_X86 > PCI_IO_OPS Done https://review.coreboot.org/c/coreboot/+/56789/comment/9359427c_4fba13b3 PS36, Line 417: select PCI_COMMON > Shouldn't we use "depends on PCI" here? PCI tag in libpayload only means that the common PCIe interface, I think we should select it instead of depends on it. File payloads/libpayload/drivers/pci_io_ops.c: https://review.coreboot.org/c/coreboot/+/56789/comment/6e11433d_86303ac2 PS35, Line 33: device > Take the chance to change this to "dev" for consistency. Done File payloads/libpayload/drivers/pci_map_bus_ops.c: https://review.coreboot.org/c/coreboot/+/56789/comment/29b4eccb_0df02398 PS35, Line 38: addr > void *addr = ... […] Done File payloads/libpayload/drivers/pci_map_bus_ops.c: https://review.coreboot.org/c/coreboot/+/56789/comment/48c427e5_9b1c4fae PS37, Line 3: 2008 Advanced Micro Devices, Inc. : * Copyright (C) 2008 coresystems GmbH > Please correct these. Done File payloads/libpayload/include/pci.h: https://review.coreboot.org/c/coreboot/+/56789/comment/e6271448_07e88fd2 PS35, Line 105: u32 device > Take the chance to change this to "pcidev_t dev" for consistency. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 40 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 06:46:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56794 to look at the new patch set (#41). Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... libpayload/pci: Add PCIe interfaces for MediaTek platform Add PCIe configuration interfaces for MediaTek platform. The register base address of PCIe hardware might be different when it's a non-x86 platform, add 'pci_update_hw_base()' interface for users to update its base address to access PCIe hardware correctly. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pcie_mediatek.c M payloads/libpayload/include/pci.h 4 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56794/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 41 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56789 to look at the new patch set (#40). Change subject: libpayload/pci: Add support for bus mapping ...................................................................... libpayload/pci: Add support for bus mapping Move the common APIs to pci_common.c and others to the chip related file. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pci_io_ops.c A payloads/libpayload/drivers/pci_map_bus_ops.c R payloads/libpayload/drivers/pci_ops.c M payloads/libpayload/include/pci.h 6 files changed, 136 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56789/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 40 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree for moli
by Raihow Shi (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: YH Lin, Subrata Banik, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63080 ) Change subject: mb/google/brask/variants/moli: update overridetree for moli ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63080/comment/78655de1_9364c448 PS7, Line 8: option STORAGE_NVME 0 : option STORAGE_EMMC 1 > Are these going to be used to enable / disable devices ? Currently, these used to distinguish SSD or eMMC for the b/220039297, and we also have FW_CONFIG in CL: https://chrome-internal-review.googlesource.com/c/chromeos/project/brask/mo…. -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 7 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 30 Mar 2022 06:03:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2022