coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56794 ) Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... Patch Set 42: (1 comment) File payloads/libpayload/drivers/pcie_mediatek.c: https://review.coreboot.org/c/coreboot/+/56794/comment/21fad88d_8447d5f7 PS38, Line 22: pcie_base = base; > The base address can be stored in the coreboot table. […] I think maybe we can use the config data from device tree so that we don't need to add macros to define it. I'll try to create a similar patch, thanks for the information. -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 42 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 08:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Yu-Ping Wu (Code Review) 30 Mar '22

30 Mar '22

1 0

Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Yu-Ping Wu (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 41: (4 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/cd675fad_1aa7addb PS36, Line 411: select PCI_COMMON : default n > In that case, PCI_IO_OPS should be set to "default n", I'm not sure if this can work properly on x86 […] See my comment above. https://review.coreboot.org/c/coreboot/+/56789/comment/16f0f265_72fece2a PS36, Line 417: select PCI_COMMON > PCI tag in libpayload only means that the common PCIe interface, I think we should select it instead […] The value of PCI_IO_OPS doesn't matter when PCI is disabled, so PCI_IO_OPS should depend on "PCI=y". I tried config PCI_IO_OPS depends on PCI default y if ARCH_X86 default n config PCIE_MEDIATEK depends on !PCI_IO_OPS default n and it worked as expected: 1. MTK: Enable *both* PCI and PCIE_MEDIATEK from the overlay 2. x86: When PCI is enabled, PCI_IO_OPS will be selected automatically. 3. Others: When PCI is enabled but PCIE_MEDIATEK is not, pci_map_bus() will be undefined. File payloads/libpayload/drivers/pci_map_bus_ops.c: https://review.coreboot.org/c/coreboot/+/56789/comment/434aa632_6f3f75e4 PS35, Line 38: | > The cfg_base should be 4K alignment, and the range of reg should be 0 ~ 4K for each device's config […] Okay, I think the current implementation is fine. File payloads/libpayload/include/pci.h: https://review.coreboot.org/c/coreboot/+/56789/comment/a9a072ac_6104afb3 PS40, Line 105: u32 pcidev_t -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 41 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 07:56:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: implement ioc driver
by Wonkyu Kim (Code Review) 30 Mar '22

30 Mar '22

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63198 ) Change subject: soc/intel/common: implement ioc driver ...................................................................... soc/intel/common: implement ioc driver DMI interface is moved to IOC in MTL Reference: 643504 MTL FAS section 7.5.2 and reference FSP code. https://github.com/otcshare/CCG-MTL-Generic-PSS/blob/master/ ClientOneSiliconPkg/IpBlock/Ioc/IncludePrivate/Register/IocRegs.h TEST=Build and boot to OS for TGL and MTL Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 --- M src/soc/intel/common/block/gpmr/Kconfig M src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/gpmr.h A src/soc/intel/common/block/include/intelblocks/ioc.h A src/soc/intel/common/block/include/intelblocks/ioc_reg.h A src/soc/intel/common/block/ioc/Kconfig A src/soc/intel/common/block/ioc/Makefile.inc A src/soc/intel/common/block/ioc/ioc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/pch/lockdown/lockdown.c 11 files changed, 133 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/63198/1 diff --git a/src/soc/intel/common/block/gpmr/Kconfig b/src/soc/intel/common/block/gpmr/Kconfig index b307493..7d21687 100644 --- a/src/soc/intel/common/block/gpmr/Kconfig +++ b/src/soc/intel/common/block/gpmr/Kconfig @@ -1,6 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_GPMR bool - depends on SOC_INTEL_COMMON_BLOCK_DMI + depends on SOC_INTEL_COMMON_BLOCK_DMI || SOC_INTEL_COMMON_BLOCK_IOC help - Mirror GPMR registers for IO/MMIO to their corresponding DMI registers. + Mirror GPMR registers for IO/MMIO to their corresponding DMI/IOC registers. Required for extending BIOS region. diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c index 532d619..306c209 100644 --- a/src/soc/intel/common/block/gpmr/gpmr.c +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -8,13 +8,19 @@ /* GPMR Register read given offset */ static uint32_t gpmr_read32(uint16_t offset) { - return pcr_read32(PID_DMI, offset); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + return ioc_reg_read32(offset); + else + return pcr_read32(PID_DMI, offset); } /* GPMR Register write given offset and val */ static void gpmr_write32(uint16_t offset, uint32_t val) { - return pcr_write32(PID_DMI, offset, val); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + return ioc_reg_write32(offset, val); + else + return pcr_write32(PID_DMI, offset, val); } /* Check for available free gpmr */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpmr.h b/src/soc/intel/common/block/include/intelblocks/gpmr.h index c9cd3bc..64d37c5 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpmr.h +++ b/src/soc/intel/common/block/include/intelblocks/gpmr.h @@ -5,6 +5,19 @@ #include <types.h> #include <intelblocks/dmi.h> +#include <intelblocks/ioc.h> + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOC) + +#define MAX_GPMR_REGS IOC_MAX_GPMR_REGS +#define GPMR_OFFSET IOC_GPMR_OFFSET +#define GPMR_LIMIT_MASK IOC_GPMR_LIMIT_MASK +#define GPMR_BASE_SHIFT IOC_GPMR_BASE_SHIFT +#define GPMR_BASE_MASK IOC_GPMR_BASE_MASK +#define GPMR_DID_OFFSET IOC_GPMR_DID_OFFSET +#define GPMR_EN IOC_GPMR_EN + +#else #define MAX_GPMR_REGS PCR_MAX_GPMR_REGS #define GPMR_OFFSET PCR_GPMR_OFFSET @@ -14,6 +27,8 @@ #define GPMR_DID_OFFSET PCR_GPMR_DID_OFFSET #define GPMR_EN PCR_GPMR_EN +#endif + enum cb_err enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); #endif /* SOC_INTEL_COMMON_BLOCK_GPMR_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/ioc.h b/src/soc/intel/common/block/include/intelblocks/ioc.h new file mode 100644 index 0000000..c5d5926 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/ioc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_IOC_H +#define SOC_INTEL_COMMON_BLOCK_IOC_H + +#include <types.h> + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOC_REG_HEADER_OVERRIDE) +/* Overridden definitions */ +#include <soc/ioc_reg.h> +#else +/*Default definitions */ +#include <intelblocks/ioc_reg.h> +#endif + +void ioc_reg_write32(uint32_t offset, uint32_t value); +uint32_t ioc_reg_read32(uint32_t offset); + +#endif /* SOC_INTEL_COMMON_BLOCK_IOC_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/ioc_reg.h b/src/soc/intel/common/block/include/intelblocks/ioc_reg.h new file mode 100644 index 0000000..5428949 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/ioc_reg.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _IOC_REG_H_ +#define _IOC_REG_H_ + +#define R_IOC_CFG_LPCLGIR1 0x7a30 +#define R_IOC_CFG_LPCGMR 0x7A40 +#define R_IOC_CFG_GCS 0x7a4C /* Generic Control and Status */ +#define B_IOC_CFG_BILD 0x1 /* BIOS interface Lockdown */ +#define R_IOC_CFG_LPCIOD 0x7a70 /* LPC I/O Decode Ranges */ +#define R_IOC_CFG_LPCIOE 0x7a74 /* LPC I/O Enables */ +#define R_IOC_CFG_TCOBASE 0x7a78 /* TCO Base Address */ +#define B_IOC_CFG_TCOBASE_TCOBA 0xFFE0 +#define R_IOC_CFG_GPMR1 0x7A7C +#define R_IOC_CFG_GPMR1DID 0x7A80 + +#define IOC_MAX_GPMR_REGS 3 + +#define IOC_GPMR_OFFSET(x) (R_IOC_CFG_GPMR1 + (x) * 8) +#define IOC_GPMR_LIMIT_MASK 0xffff0000 +#define IOC_GPMR_BASE_SHIFT 16 +#define IOC_GPMR_BASE_MASK 0xffff + +#define IOC_GPMR_DID_OFFSET(x) (R_IOC_CFG_GPMR1DID + (x) * 8) +#define IOC_GPMR_EN BIT(31) + +#endif diff --git a/src/soc/intel/common/block/ioc/Kconfig b/src/soc/intel/common/block/ioc/Kconfig new file mode 100644 index 0000000..223af43 --- /dev/null +++ b/src/soc/intel/common/block/ioc/Kconfig @@ -0,0 +1,10 @@ +config SOC_INTEL_COMMON_BLOCK_IOC + bool + help + Intel Processor common IO Cache(IOC) + +config SOC_INTEL_COMMON_BLOCK_IOC_REG_HEADER_OVERRIDE + bool + help + ioc register offset override + diff --git a/src/soc/intel/common/block/ioc/Makefile.inc b/src/soc/intel/common/block/ioc/Makefile.inc new file mode 100644 index 0000000..5896534 --- /dev/null +++ b/src/soc/intel/common/block/ioc/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOC) += ioc.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOC) += ioc.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOC) += ioc.c diff --git a/src/soc/intel/common/block/ioc/ioc.c b/src/soc/intel/common/block/ioc/ioc.c new file mode 100644 index 0000000..3f2374c --- /dev/null +++ b/src/soc/intel/common/block/ioc/ioc.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/ioc.h> +#include <device/mmio.h> +#include <soc/iomap.h> + +void ioc_reg_write32(uint32_t offset, uint32_t value) +{ + write32((void *)MCH_BASE_ADDRESS + offset, value); +} + +uint32_t ioc_reg_read32(uint32_t offset) +{ + uint32_t value; + value = read32((void *)MCH_BASE_ADDRESS + offset); + return value; +} + diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 1393714..d75a44c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -9,6 +9,7 @@ #include <device/pci_ops.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/ioc.h> #include <intelblocks/pcr.h> #include <lib.h> #include "lpc_def.h" @@ -24,7 +25,9 @@ reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); io_enables |= reg_io_enables; pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + ioc_reg_write32(R_IOC_CFG_LPCIOE, io_enables); + else if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); return io_enables; @@ -42,7 +45,9 @@ reg_io_ranges = lpc_get_fixed_io_decode() & ~mask; io_ranges |= reg_io_ranges & mask; pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + ioc_reg_write32(R_IOC_CFG_LPCIOD, io_ranges); + else if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges); return io_ranges; @@ -112,7 +117,10 @@ lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + ioc_reg_write32(R_IOC_CFG_LPCLGIR1 + lgir_reg_num * 4, lgir); + else if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir); printk(BIOS_DEBUG, @@ -147,7 +155,9 @@ lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN; pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + ioc_reg_write32(R_IOC_CFG_LPCGMR, lgmr); + else if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr); } @@ -248,7 +258,9 @@ /* Set in PCI generic decode range registers */ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + ioc_reg_write32(R_IOC_CFG_LPCLGIR1 + i * 4, gen_io_dec[i]); + else if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]); } } diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 518541b..1d21e2b 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -10,6 +10,7 @@ #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> +#include <intelblocks/ioc.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -122,10 +123,11 @@ /* Enable TCO in SMBUS */ pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN); - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); + /* Program "TCO Base Address */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + ioc_reg_write32(R_IOC_CFG_TCOBASE, tcobase | TCOEN); + else + pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); } /* diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 5ab0611..800eee5 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -5,6 +5,7 @@ #include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> +#include <intelblocks/ioc.h> #include <intelpch/lockdown.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -27,6 +28,10 @@ static void dmi_lockdown_cfg(void) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + ioc_reg_write32(R_IOC_CFG_GCS, + ioc_reg_read32(R_IOC_CFG_GCS)|B_IOC_CFG_BILD); + else { /* * GCS reg of DMI * @@ -37,13 +42,14 @@ * "0b": SPI * "1b": LPC/eSPI */ - pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); + pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); /* * Set Secure Register Lock (SRL) bit in DMI control register to lock * DMI configuration. */ - pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); + pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); + } } static void fast_spi_lockdown_cfg(int chipset_lockdown) -- To view, visit https://review.coreboot.org/c/coreboot/+/63198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Gerrit-Change-Number: 63198 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 41: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/728db5fd_717acdf9 PS36, Line 411: select PCI_COMMON : default n > In that case, PCI_IO_OPS should be set to "default n", I'm not sure if this can work properly on x86 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 41 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 07:49:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56789 to look at the new patch set (#41). Change subject: libpayload/pci: Add support for bus mapping ...................................................................... libpayload/pci: Add support for bus mapping Move the common APIs to pci_common.c and others to the chip related file. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pci_io_ops.c A payloads/libpayload/drivers/pci_map_bus_ops.c R payloads/libpayload/drivers/pci_ops.c M payloads/libpayload/include/pci.h 6 files changed, 135 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56789/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 41 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Documentation: gpio: Provide minor fixes to the table
by Subrata Banik (Code Review) 30 Mar '22

30 Mar '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63177 ) Change subject: Documentation: gpio: Provide minor fixes to the table ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Landed early to unbreak the table on the doc site Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/63177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd8265b92b5ef0dcabb754371591477ca19c39be Gerrit-Change-Number: 63177 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 07:26:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation: gpio: Provide minor fixes to the table
by Michael Niewöhner (Code Review) 30 Mar '22

30 Mar '22

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63177 ) Change subject: Documentation: gpio: Provide minor fixes to the table ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Landed early to unbreak the table on the doc site -- To view, visit https://review.coreboot.org/c/coreboot/+/63177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd8265b92b5ef0dcabb754371591477ca19c39be Gerrit-Change-Number: 63177 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 07:19:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation: gpio: Provide minor fixes to the table
by Michael Niewöhner (Code Review) 30 Mar '22

30 Mar '22

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63177 ) Change subject: Documentation: gpio: Provide minor fixes to the table ...................................................................... Documentation: gpio: Provide minor fixes to the table This patch fixes the table issue in markdown file identified with commit 96481066 (Documentation: gpio: Update table as per coreboot guidelines). BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ifd8265b92b5ef0dcabb754371591477ca19c39be Reviewed-on: https://review.coreboot.org/c/coreboot/+/63177 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M Documentation/getting_started/gpio.md 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 216ba5d..fd0267a 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -176,7 +176,7 @@ | | 00 - Power Good | Warm Reset | N | N | | | (GPP: RSMRST, +----------------+-------------+-------------+ | | GPD: DSW_PWROK) | Cold Reset | N | N | -| |----------------+-------------+-------------+ +| +----------------+-------------+-------------+ | | S3/S4/S5 | N | N | | +----------------+-------------+-------------+ | | Global Reset | N | N | @@ -209,17 +209,17 @@ | +----------------+-------------+-------------+ | | G3 | Y | Y | +------------------------+----------------+-------------+-------------+ -| | 11 - Resume Reset | Warm Reset | - | N | +| | 11 - Resume Reset | Warm Reset | n/a | N | | | (GPP: Reserved, +----------------+-------------+-------------+ -| | GPD: RSMRST) | Cold Reset | - | N | +| | GPD: RSMRST) | Cold Reset | n/a | N | | +----------------+-------------+-------------+ -| | S3/S4/S5 | - | N | +| | S3/S4/S5 | n/a | N | | +----------------+-------------+-------------+ -| | Global Reset | - | N | +| | Global Reset | n/a | N | | +----------------+-------------+-------------+ -| | Deep Sx | - | Y | +| | Deep Sx | n/a | Y | | +----------------+-------------+-------------+ -| | G3 | - | Y | +| | G3 | n/a | Y | +------------------------+----------------+-------------+-------------+ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd8265b92b5ef0dcabb754371591477ca19c39be Gerrit-Change-Number: 63177 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Makefile.inc: Explicitly delete coreboot.pre
by Michael Niewöhner (Code Review) 30 Mar '22

30 Mar '22

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62922 ) Change subject: Makefile.inc: Explicitly delete coreboot.pre ...................................................................... Makefile.inc: Explicitly delete coreboot.pre coreboot.pre doesn't follow the standard Make conventions. It gets modified by multiple rules, and thus we can't compute the dependencies correctly. This means we need to manually delete it before starting the dependency calculations. i.e., Building firmware with the seabios payload now works correctly. Fixes: dd6efce934f ("Makefile: Add .SECONDARY") Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If5fa3f0b8d314369a044658e452bd75bc7709397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index 929c236..377ddff 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1116,6 +1116,10 @@ TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) endif +# coreboot.pre doesn't follow the standard Make conventions. It gets modified +# by multiple rules, and thus we can't compute the dependencies correctly. +$(shell rm -f $(obj)/coreboot.pre) + ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5fa3f0b8d314369a044658e452bd75bc7709397 Gerrit-Change-Number: 62922 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022