coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Add early_init for passing data across stages
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63019 ) Change subject: soc/mediatek: Add early_init for passing data across stages ...................................................................... Patch Set 12: (2 comments) File src/soc/mediatek/common/early_init.c: https://review.coreboot.org/c/coreboot/+/63019/comment/5350e25b_7ad05e11 PS12, Line 34: uint64_t > The signature of mono_time_diff_microseconds is long. […] Send another patch to fix it, thanks! https://review.coreboot.org/c/coreboot/+/63190/1 https://review.coreboot.org/c/coreboot/+/63019/comment/d4205fbd_f0af5d20 PS12, Line 42: memset(&cur_time, 0, sizeof(cur_time)); > would a struct mono_time cur_time = {0}; in line 37 do the same as this memset? if so, that might be […] Indeed, send another patch to fix it, thanks! https://review.coreboot.org/c/coreboot/+/63190/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 30 Mar 2022 01:41:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Fix function type and initialize structure to zero
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63190 ) Change subject: soc/mediatek: Fix function type and initialize structure to zero ...................................................................... soc/mediatek: Fix function type and initialize structure to zero Fix function type to comply with the data type of return value, and initialize structure to zero to replace memset. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Fixes: commit 41faa22 (soc/mediatek: Add early_init for passing data across stages) Change-Id: I7c361828362c2dfec91358ad8a420f5360243da0 --- M src/soc/mediatek/common/early_init.c M src/soc/mediatek/common/include/soc/early_init.h 2 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63190/1 diff --git a/src/soc/mediatek/common/early_init.c b/src/soc/mediatek/common/early_init.c index 329663c..55ba447 100644 --- a/src/soc/mediatek/common/early_init.c +++ b/src/soc/mediatek/common/early_init.c @@ -31,16 +31,14 @@ timer_monotonic_get(&data->init_time[init_type]); } -uint64_t early_init_get_elapsed_time_us(enum early_init_type init_type) +long early_init_get_elapsed_time_us(enum early_init_type init_type) { struct early_init_data *data = find_early_init(); - struct mono_time cur_time; + struct mono_time cur_time = {0}; if (!data) return 0; - memset(&cur_time, 0, sizeof(cur_time)); - /* If early init data was never saved */ if (!memcmp(&data->init_time[init_type], &cur_time, sizeof(cur_time))) return 0; diff --git a/src/soc/mediatek/common/include/soc/early_init.h b/src/soc/mediatek/common/include/soc/early_init.h index 2811b0d..533dffd 100644 --- a/src/soc/mediatek/common/include/soc/early_init.h +++ b/src/soc/mediatek/common/include/soc/early_init.h @@ -21,6 +21,6 @@ void early_init_clear(void); void early_init_save_time(enum early_init_type init_type); -uint64_t early_init_get_elapsed_time_us(enum early_init_type init_type); +long early_init_get_elapsed_time_us(enum early_init_type init_type); #endif /* SOC_MEDIATEK_EARLY_INIT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c361828362c2dfec91358ad8a420f5360243da0 Gerrit-Change-Number: 63190 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt
by Rob Barnes (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Robert Zieba, Chris Wang, Karthik Ramasubramanian, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63132 ) Change subject: mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63132/comment/6a956efa_d28afd6a PS4, Line 16: SPD_SOURCES += $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/K4U6E3S4AB-MGCL.hex # ID = 9(0b1001) Parts = K4U6E3S4AB-MGCL > Since I saw that doesn't include that specific part number in the separated SPD data. […] Yes we need to add new support in part_id_gen tool. This will take a few days. This change is needed to unblock the project. I'm going to +2 this change while we add support to part_id_gen in parallel (b/224884904). We will need to manually maintain this patch to this Makefile until part_id_gen is updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/63132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94 Gerrit-Change-Number: 63132 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 30 Mar 2022 01:21:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/port_descriptors: update DDI descriptors
by Felix Held (Code Review) 30 Mar '22

30 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63163 ) Change subject: mb/amd/chausie/port_descriptors: update DDI descriptors ...................................................................... mb/amd/chausie/port_descriptors: update DDI descriptors Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63163 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/chausie/port_descriptors.c 1 file changed, 10 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c index 02e82b8..2609961 100644 --- a/src/mainboard/amd/chausie/port_descriptors.c +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -48,30 +48,30 @@ }; static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = { - { /* DDI0 - DP */ - .connector_type = DDI_DP, + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, .aux_index = DDI_AUX1, .hdp_index = DDI_HDP1 }, - { /* DDI1 - HDMI */ + { /* DDI1 - HDMI - TODO: add runtime HDMI/DP connector card detection */ .connector_type = DDI_HDMI, .aux_index = DDI_AUX2, .hdp_index = DDI_HDP2 }, - { /* DDI2 */ - .connector_type = DDI_UNUSED_TYPE, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP, .aux_index = DDI_AUX3, .hdp_index = DDI_HDP3, }, { /* DDI3 - DP (type C) */ .connector_type = DDI_DP, - .aux_index = DDI_AUX3, - .hdp_index = DDI_HDP3, - }, - { /* DDI4 - DP (type C) */ - .connector_type = DDI_DP, .aux_index = DDI_AUX4, .hdp_index = DDI_HDP4, + }, + { /* DDI4 - unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c Gerrit-Change-Number: 63163 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/chausie/devicetree: update PCI root ports
by Felix Held (Code Review) 30 Mar '22

30 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63162 ) Change subject: mb/amd/chausie/devicetree: update PCI root ports ...................................................................... mb/amd/chausie/devicetree: update PCI root ports Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the actual hardware configuration. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I378c620abb6e52de680669b6edd228874153e399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/chausie/devicetree.cb 1 file changed, 3 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 7f37be2..85e9c08 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -28,12 +28,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # NVMe - device ref gpp_bridge_1 on end - device ref gpp_bridge_2 on end # WWAN - device ref gpp_bridge_3 on end # LAN - device ref gpp_bridge_4 on end # WLAN - device ref gpp_bridge_5 on end + device ref gpp_bridge_0 on end # GBE + device ref gpp_bridge_1 on end # WIFI + device ref gpp_bridge_2 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) -- To view, visit https://review.coreboot.org/c/coreboot/+/63162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I378c620abb6e52de680669b6edd228874153e399 Gerrit-Change-Number: 63162 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/chausie/port_descriptors: update DXIO descriptors
by Felix Held (Code Review) 30 Mar '22

30 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63161 ) Change subject: mb/amd/chausie/port_descriptors: update DXIO descriptors ...................................................................... mb/amd/chausie/port_descriptors: update DXIO descriptors Change the DXIO descriptors to match the default PCIe lane mapping on the chausie board. With this configuration and a board-level rework to bypass the EC control of the NVMe SSD power supply rail, this configuration results in the SSD being detected on the root port on bus 0 device 2 function 3 and usable as boot device. This was also validated against the schematics revision B. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/chausie/port_descriptors.c 1 file changed, 22 insertions(+), 67 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c index 46afa77..02e82b8 100644 --- a/src/mainboard/amd/chausie/port_descriptors.c +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -5,91 +5,46 @@ #include <types.h> static const fsp_dxio_descriptor chausie_czn_dxio_descriptors[] = { - { /* MXM */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 23, - .device_number = 1, - .function_number = 1, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* SSD */ + { /* GBE*/ .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 0, - .end_logical_lane = 1, + .end_logical_lane = 0, .device_number = 2, .function_number = 1, + .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5, - .gpio_group_id = GPIO_40, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + .link_aspm = 2, + .link_hotplug = 3, + .clk_req = CLK_REQ3, }, - { /* DT */ + { /* WIFI */ .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 4, - .end_logical_lane = 4, + .start_logical_lane = 1, + .end_logical_lane = 1, .device_number = 2, .function_number = 2, + .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ4_GFX, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* WWAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 5, - .end_logical_lane = 5, - .device_number = 2, - .function_number = 3, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* LAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 6, - .end_logical_lane = 6, - .device_number = 2, - .function_number = 4, - .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, .clk_req = CLK_REQ1, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, - { /* WLAN */ + { /* NVMe SSD */ .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 7, - .end_logical_lane = 7, - .device_number = 2, - .function_number = 5, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* TB */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 8, - .end_logical_lane = 11, - .device_number = 2, - .function_number = 6, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* SATA */ - .engine_type = SATA_ENGINE, - .port_present = true, .start_logical_lane = 2, .end_logical_lane = 3, - .channel_type = SATA_CHANNEL_LONG, - } + .device_number = 2, + .function_number = 3, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ0, + }, }; static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Gerrit-Change-Number: 63161 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support for dojo
by Jianjun Wang (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Jianjun Wang. Hello Hung-Te Lin, Shelley Chen, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62360 to look at the new patch set (#27). Change subject: mb/google/cherry: Add PCIe domain support for dojo ...................................................................... mb/google/cherry: Add PCIe domain support for dojo Add override device tree for dojo and add PCIe domain support. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 --- M src/mainboard/google/cherry/Kconfig A src/mainboard/google/cherry/variants/dojo/overridetree.cb 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62360/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 27 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add Kconfig SOC_INTEL_CSE_SET_EOP
by Wonkyu Kim (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: John Zhao, Tim Wawrzynczak, EricR Lai. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63159 ) Change subject: soc/intel/common: Add Kconfig SOC_INTEL_CSE_SET_EOP ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib52404d9ad4c01a460e4cfef331c529d2a53337a Gerrit-Change-Number: 63159 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 00:23:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow retrieving FSP timestamp information
by Eric Lai (Code Review) 30 Mar '22

30 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62943 ) Change subject: soc/intel/alderlake: Allow retrieving FSP timestamp information ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568f18c6bc4f54e87f8763a331796f4a72d4c976 Gerrit-Change-Number: 62943 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 00:13:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: update GPIOs for moli
by Felix Held (Code Review) 30 Mar '22

30 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62802 ) Change subject: mb/google/brask/variants/moli: update GPIOs for moli ...................................................................... mb/google/brask/variants/moli: update GPIOs for moli Follow the Moli GPIO Table_20220324.xlsx to update it. 1.Set A15 as the default value. 2.Set A14, A19 NC. 3.Set C3, C4 as the default value. 4.Set D9 as the default value. 5.Set E5, E13 as the default value. 6.Set R4, R5 as the default value. 7.Update E14. 8.Set E12 as the default value. 9.Set D16 as the default value. BUG=b:220821454 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Ia54256244111a99cb130b74f78c37815099a021a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/moli/gpio.c 1 file changed, 8 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/gpio.c b/src/mainboard/google/brya/variants/moli/gpio.c index 6ba605e..59bb1df 100644 --- a/src/mainboard/google/brya/variants/moli/gpio.c +++ b/src/mainboard/google/brya/variants/moli/gpio.c @@ -7,8 +7,12 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { - /* A15 : USB_OC2# ==> DDIC_DP_HPD4 */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> DDIC_DP_HPD4 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* A21 : DDPC_CTRCLK ==> DDIC_DP_CTRCLK */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* A22 : DDPC_CTRLDATA ==> DDIC_DP_CTRLDATA */ @@ -19,30 +23,17 @@ /* B3 : PROC_GP2 ==> EMMC_PERST_L */ PAD_CFG_GPO(GPP_B3, 1, DEEP), - /* C3 : SML0CLK ==> PCH_SML0_CLK */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : SML0DATA ==> PCH_SML0_DATA */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* D9 : ISH_SPI_CS# ==> NC */ - PAD_NC(GPP_D9, NONE), /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ PAD_CFG_GPO(GPP_D14, 1, DEEP), - /* D16 : ISH_UART0_CTS# ==> USB_A2_RT_RST_ODL */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), /* E1 : THC0_SPI1_IO2 ==> B2B_HDMICARD_DETN */ PAD_CFG_GPI(GPP_E1, NONE, DEEP), /* E2 : THC0_SPI1_IO3 ==> B2B_DPCARD_DETN */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), - /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ - PAD_CFG_GPO(GPP_E5, 1, DEEP), - /* E12 : THC0_SPI1_IO1 ==> B2B_USBCCARD_DETN */ - PAD_NC(GPP_E12, NONE), - /* E13 : THC0_SPI1_IO2 ==> B2B_SERIAL_DETN */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E14 : DDSP_HPDA ==> HDMI2_HPD */ + PAD_CFG_GPI(GPP_E14, NONE, DEEP), /* E20 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E21 : DDP2_CTRLDATA ==> NC */ @@ -51,10 +42,6 @@ /* H19 : SRCCLKREQ4# ==> LAN_I225V_CLKREQ_ODL */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), - /* R4 : HDA_RST# ==> NC */ - PAD_NC(GPP_R4, NONE), - /* R5 : HDA_SDI1 ==> NC */ - PAD_NC(GPP_R5, NONE), /* R6 : I2S2_TXD ==> NC */ PAD_NC(GPP_R6, NONE), /* R7 : I2S2_RXD ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia54256244111a99cb130b74f78c37815099a021a Gerrit-Change-Number: 62802 Gerrit-PatchSet: 13 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit March 2022