coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

1 participants
7066 discussions

Change in coreboot[master]: mb/intel/adlrvp: TEST Enable TME from devicetree
by Ronak Kanabar (Code Review) 02 Feb '22

02 Feb '22

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61546 ) Change subject: mb/intel/adlrvp: TEST Enable TME from devicetree ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/61546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If656b054f4913779da927ee4df83d4f6fbcc9b8d Gerrit-Change-Number: 61546 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by EricR Lai (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:48:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: TEST Enable TME from devicetree
by Ronak Kanabar (Code Review) 02 Feb '22

02 Feb '22

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61546 ) Change subject: mb/intel/adlrvp: TEST Enable TME from devicetree ...................................................................... mb/intel/adlrvp: TEST Enable TME from devicetree This patch is needed when following patch is used for test. https://review.coreboot.org/c/coreboot/+/61492 Change-Id: If656b054f4913779da927ee4df83d4f6fbcc9b8d Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_n.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/61546/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 9bd99b1..0d357dc 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -16,6 +16,9 @@ # Sagv Configuration register "SaGv" = "SaGv_Enabled" + #Enable Total Memory Encryption + register "enable_tme" = "true" + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index f013596..79cb57c 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -16,6 +16,9 @@ # Sagv Configuration register "SaGv" = "SaGv_Enabled" + #Enable Total Memory Encryption + register "enable_tme" = "true" + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If656b054f4913779da927ee4df83d4f6fbcc9b8d Gerrit-Change-Number: 61546 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/cannonlake: Forbid FSP from disabling HECI1
by Lean Sheng Tan (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61455 ) Change subject: soc/intel/cannonlake: Forbid FSP from disabling HECI1 ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Gerrit-Change-Number: 61455 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:41:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Use PMC IPC to disable HECI1
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61458 ) Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1 ...................................................................... soc/intel/alderlake: Use PMC IPC to disable HECI1 This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Alder Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61458 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/finalize.c M src/soc/intel/alderlake/smihandler.c 3 files changed, 3 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fa95088..863150e 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -78,6 +78,7 @@ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 589ea59..880e1e0 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -106,6 +106,8 @@ tbt_finalize(); sa_finalize(); heci_finalize(); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + heci1_disable(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 61fecdf..e1fc5a0 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -1,28 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_def.h> -#include <intelblocks/cse.h> #include <intelblocks/smihandler.h> #include <soc/soc_chip.h> #include <soc/pci_devs.h> #include <soc/pm.h> -/* - * Specific SOC SMI handler during ramstage finalize phase - * - * BIOS can't make CSME function disable as is due to POSTBOOT_SAI - * restriction in place from ADP chipset. Hence create SMI Handler to - * perform CSME function disabling logic during SMM mode. - */ -void smihandler_soc_at_finalize(void) -{ - if (!CONFIG(HECI_DISABLE_USING_SMM)) - return; - - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci1_disable(); -} - int smihandler_soc_disable_busmaster(pci_devfn_t dev) { /* Skip disabling PMC bus master to keep IO decode enabled */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Gerrit-Change-Number: 61458 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/tigerlake: Use PMC IPC to disable HECI1
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61457 ) Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1 ...................................................................... soc/intel/tigerlake: Use PMC IPC to disable HECI1 This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/smihandler.c 3 files changed, 4 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b324a04..7a8b01b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 @@ -84,7 +85,6 @@ select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM config MAX_CPUS int diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index b50529b..1067278 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -12,6 +12,7 @@ #include <cpu/x86/smm.h> #include <device/mmio.h> #include <device/pci.h> +#include <intelblocks/cse.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> @@ -64,6 +65,8 @@ apm_control(APM_CNT_FINALIZE); tbt_finalize(); sa_finalize(); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + heci1_disable(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 843733f..e1fc5a0 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -1,25 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_def.h> -#include <intelblocks/cse.h> #include <intelblocks/smihandler.h> #include <soc/soc_chip.h> #include <soc/pci_devs.h> #include <soc/pm.h> -/* - * Specific SOC SMI handler during ramstage finalize phase - * - * BIOS can't make CSME function disable as is due to POSTBOOT_SAI - * restriction in place from TGP chipset. Hence create SMI Handler to - * perform CSME function disabling logic during SMM mode. - */ -void smihandler_soc_at_finalize(void) -{ - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) - heci1_disable(); -} - int smihandler_soc_disable_busmaster(pci_devfn_t dev) { /* Skip disabling PMC bus master to keep IO decode enabled */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Gerrit-Change-Number: 61457 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/jasperlake: Use SBI msg to disable HECI1
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61456 ) Change subject: soc/intel/jasperlake: Use SBI msg to disable HECI1 ...................................................................... soc/intel/jasperlake: Use SBI msg to disable HECI1 Select HECI_DISABLE_USING_SMM config for Jasper Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61456 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 556b2f2..8fb0f49 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -64,7 +64,7 @@ select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO_2 - select HECI_DISABLE_USING_SMM + select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 3dca4a2..f2294fe 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -16,7 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 Gerrit-Change-Number: 61456 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/cannonlake: Use SBI msg to disable HECI1
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61451 ) Change subject: soc/intel/cannonlake: Use SBI msg to disable HECI1 ...................................................................... soc/intel/cannonlake: Use SBI msg to disable HECI1 Select HECI_DISABLE_USING_SMM config for Cannon Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61451 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/smihandler.c 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4a084a3..f85cd15 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -109,6 +109,7 @@ config DISABLE_HECI1_AT_PRE_BOOT default y if MAINBOARD_HAS_CHROMEOS + select HECI_DISABLE_USING_SMM config MAX_CPUS int diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index ac25990..88b58e8 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -16,7 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 Gerrit-Change-Number: 61451 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/apollolake: Use PCR write to disable HECI1
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61444 ) Change subject: soc/intel/apollolake: Use PCR write to disable HECI1 ...................................................................... soc/intel/apollolake: Use PCR write to disable HECI1 Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Apollo Lake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61444 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/cse.c 2 files changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d3f7332..cd0abf7 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -73,6 +73,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GRAPHICS + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 29d0a5e..7d1e6e7 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -192,7 +192,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) -static void disable_heci1(void) +void soc_disable_heci1_using_pcr(void) { pcr_or32(PID_PSF3, PSF3_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); @@ -207,7 +207,7 @@ * anymore. */ if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - disable_heci1(); + heci1_disable(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fpf_blown, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/61444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e Gerrit-Change-Number: 61444 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/skylake: Use PCR write to disable HECI1
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61433 ) Change subject: soc/intel/skylake: Use PCR write to disable HECI1 ...................................................................... soc/intel/skylake: Use PCR write to disable HECI1 Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Skylake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61433 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c 2 files changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index b90fdef..31e733c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -63,6 +63,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 733f037..5021595 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/cpulib.h> +#include <intelblocks/cse.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> @@ -30,7 +31,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) -static void pch_disable_heci(void) +void soc_disable_heci1_using_pcr(void) { /* unhide p2sb device */ p2sb_unhide(); @@ -60,7 +61,7 @@ /* we should disable Heci1 based on the config */ if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - pch_disable_heci(); + heci1_disable(); /* Hide p2sb device as the OS must not change BAR0. */ p2sb_hide(); -- To view, visit https://review.coreboot.org/c/coreboot/+/61433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Gerrit-Change-Number: 61433 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2022