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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 )
Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/61518/comment/bc79cf7b_fc60ccda
PS4, Line 1: config SOC_INTEL_COMMON_BLOCK_CSE
: bool
: default n
: help
: Driver for communication with Converged Security Engine (CSE)
: over Host Embedded Controller Interface (HECI)
:
: config MAX_HECI_DEVICES
: int
: default 6
:
: config DISABLE_HECI1_AT_PRE_BOOT
: bool "Disable HECI1 at the end of boot"
: depends on SOC_INTEL_COMMON_BLOCK_CSE
: default n
: help
: This config decides the state of HECI1(CSE) device at the end of boot.
: Mainboard users to select this config to make HECI1 `function disable`
: prior to handing off to payload.
:
> Sure, I will. […]
@Tim, can you please take a look if this is what you asked me to align alphabetically. or I missed completely ?
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Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, Nick Vaccaro, Werner Zeh, EricR Lai, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61518
to look at the new patch set (#5).
Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
soc/intel/{adl, common}: Add routines into CSE IA-common code
This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3 => Set CSE device state to D0I3
- heci_set_to_d0i3 => Function sets D0I3 for all HECI devices
Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.
As per PCH EDS, the HECI device count for various SoCs are:
ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL => 1 (CSE)
SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3)
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
---
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/skylake/Kconfig
M src/soc/intel/xeon_sp/Kconfig
7 files changed, 50 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/61518/5
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Change subject: mb/intel/adlrvp: Fix vbt loading error
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> The fallback path is still "vbt.bin" ? Do we have issue. […]
Yeah sounds like good idea. I will drop this CL after adding the code to fallback to 'vbt.bin'
@Subrata yes it expects to stitch vbt_adlrvp_ddr5.bin file but could not find it.
PS1:
> So the very reason, we came up with this part of code was to handle multiple vbt configurations of d […]
Hi Meera may I know do you stitch different vbt together and integrate in coreboot?
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Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/guybrush: Add the fw SPL to amdfw.cfg
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Patch Set 1: Code-Review+1
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Change subject: soc/amd/cezanne: Add the fw SPL to fw.cfg
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Change subject: amdfwtool: Add SPL support
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Change subject: mb/siemens/mc_ehl2: Disable SATA
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61414/comment/bec93bfa_5c58c2f8
PS1, Line 10: mainboard.
> You are right. This should be mentioned.
Done
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