coreboot-gerrit February 2022

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Change in coreboot[master]: src/ec: Get rid of unnecessary blank line {before,after} brace
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61556 ) Change subject: src/ec: Get rid of unnecessary blank line {before,after} brace ...................................................................... src/ec: Get rid of unnecessary blank line {before,after} brace Change-Id: I9f7c4bdd9299e686c375aced221a72994ef2d6ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/compal/ene932/ec.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_commands.h M src/ec/lenovo/h8/chip.h M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c 6 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/61556/1 diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index eb0b5ff..6389383 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -113,7 +113,6 @@ printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); pc_keyboard_init(NO_AUX_DEVICE); - } static struct device_operations ops = { diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 642c313..e9a0939 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1775,7 +1775,6 @@ int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled) { - struct ec_params_regulator_is_enabled params = { .index = index, }; diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index bbe34be..5ff1efb 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -4064,7 +4064,6 @@ */ struct ec_params_host_event { - /* Action requested by host - one of enum ec_host_event_action. */ uint8_t action; @@ -4087,7 +4086,6 @@ */ struct ec_response_host_event { - /* Mask value in case of get operation */ uint64_t value; } __ec_align4; @@ -4107,7 +4105,6 @@ }; enum ec_host_event_mask_type { - /* Main host event copy */ EC_HOST_EVENT_MAIN, diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index d1aa9fe..440c2fc 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -4,7 +4,6 @@ #define EC_LENOVO_H8EC_CHIP_H struct ec_lenovo_h8_config { - u8 config0; u8 config1; u8 config2; diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index b081ec8..bbe6490 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -18,7 +18,6 @@ { ec_write(H8_TRACKPOINT_CTRL, on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF); - } /* Controls radio-off pin in WLAN MiniPCIe slot. */ @@ -119,7 +118,6 @@ return; ec_clr_bit(0x10 + (event >> 3), event & 7); - } void h8_usb_always_on_enable(enum usb_always_on on) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index ebcbcde..c232a51 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -25,7 +25,6 @@ pmh7_register_set_bit(0x60, 3); else pmh7_register_clear_bit(0x60, 3); - } void pmh7_touchpad_enable(int onoff) -- To view, visit https://review.coreboot.org/c/coreboot/+/61556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f7c4bdd9299e686c375aced221a72994ef2d6ed Gerrit-Change-Number: 61556 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/device.h: Rmove unneeded blank line after '{'
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61555 ) Change subject: include/device/device.h: Rmove unneeded blank line after '{' ...................................................................... include/device/device.h: Rmove unneeded blank line after '{' Change-Id: I3e439a293c6b4a806cae7c6a56d28e61f7e57044 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/device.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61555/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 237d836..719d5db 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -74,7 +74,6 @@ static inline void noop_set_resources(struct device *dev) {} struct bus { - DEVTREE_CONST struct device *dev; /* This bridge device */ DEVTREE_CONST struct device *children; /* devices behind this bridge */ DEVTREE_CONST struct bus *next; /* The next bridge on this device */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e439a293c6b4a806cae7c6a56d28e61f7e57044 Gerrit-Change-Number: 61555 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/cpu: Get rid of unnecessary blank line {before,after} barce
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61554 ) Change subject: src/cpu: Get rid of unnecessary blank line {before,after} barce ...................................................................... src/cpu: Get rid of unnecessary blank line {before,after} barce Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/microcode/microcode.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/slot_1/l2_cache.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mtrr/mtrr.c 9 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/61554/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index f20d446..5e5fa81 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -313,7 +313,6 @@ /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); clock = ratio * CPU_BCLK; diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 469bd25..674a115 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -206,7 +206,6 @@ struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1); for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) { - if ((sig == entry->sig) && (pf & entry->pf)) { return ucode_updates; } diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 11899c6..9d11ef0 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -185,7 +185,6 @@ /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); clock = ratio * IRONLAKE_BCLK + ratio / 3; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index f1d03c8..08548c5 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -286,7 +286,6 @@ /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); clock = ratio * SANDYBRIDGE_BCLK; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9de6b38..42c5870 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -327,7 +327,6 @@ static void model_206ax_init(struct device *cpu) { - /* Clear out pending MCEs */ /* This should only be done on a cold boot */ mca_clear_status(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 72ece23..e66bf39 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -90,7 +90,6 @@ msr = rdmsr(IA32_PECI_CTL); msr.lo |= 1; wrmsr(IA32_PECI_CTL, msr); - } #define PIC_SENS_CFG 0x1aa diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 2a27316..fa43366 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -244,7 +244,6 @@ /* If OK then get the result from BBL_CR_ADDR */ msr = rdmsr(BBL_CR_ADDR); return (msr.lo >> 0x15); - } /* Write data into the L2 controller register at address */ @@ -270,7 +269,6 @@ */ for (i = 0; i < v2; i++) { - u32 data1, data2; // Bits legend // data1 = ffffffff @@ -352,7 +350,6 @@ */ for (cache_setting = BBLCR3_L2_SIZE_256K; cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) { - eax = bblcr3 | cache_setting; msr.lo = eax; wrmsr(BBL_CR_CTL3, msr); @@ -726,7 +723,6 @@ /* Write to all cache lines to initialize */ while (cache_size > 0) { - /* Each cache line is 32 bytes. */ cache_size -= 32; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 7780be2..bbdd598 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -329,7 +329,6 @@ udelay(10); } - } static void wait_other_cpus_stop(struct bus *cpu_bus) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index f1d36da..bc4acc4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -346,7 +346,6 @@ wrmsr(msr_index[i], fixed_msrs[i]); enable_cache(); fixed_mtrrs_hide_amd_rwdram(); - } void x86_setup_fixed_mtrrs_no_enable(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/61554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3 Gerrit-Change-Number: 61554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/security/intel: Get rid of unnecessary blank line after '{'
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61553 ) Change subject: src/security/intel: Get rid of unnecessary blank line after '{' ...................................................................... src/security/intel: Get rid of unnecessary blank line after '{' Change-Id: I90c5f175f3f407673f5b6573afc985b104e1fdd5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/intel/stm/SmmStm.c M src/security/intel/stm/StmPlatformResource.c M src/security/intel/stm/StmPlatformSmm.c M src/security/intel/txt/romstage.c 4 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/61553/1 diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index 1ebe77d..74421c7 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -38,7 +38,6 @@ #define STM_SM_MONITOR_STATE_ENABLED 1 typedef struct { - uint64_t vmcs_revision_id : 31; uint64_t always_zero : 1; uint64_t vmcs_size : 13; @@ -482,7 +481,6 @@ return -1; // INVALID_PARAMETER; if (m_stm_resources_ptr == NULL) { - // Copy EndResource for initialization m_stm_resources_ptr = stm_resource_heap; m_stm_resource_total_size = CONFIG_BIOS_RESOURCE_LIST_SIZE; @@ -648,7 +646,6 @@ if (stm_header->hw_stm_hdr.cr3_offset >= stm_header->sw_stm_hdr.static_image_size) { - // We will create page table, just in case that SINIT does not // create it. if (min_mseg_size < stm_header->hw_stm_hdr.cr3_offset diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c index 75d52a2..7b3eee1 100644 --- a/src/security/intel/stm/StmPlatformResource.c +++ b/src/security/intel/stm/StmPlatformResource.c @@ -152,7 +152,6 @@ uint32_t Index; for (Index = 0; Index < ARRAY_SIZE(msr_table); Index++) { - rsc_msr_tpl.msr_index = (uint32_t)msr_table[Index].msr_index; rsc_msr_tpl.read_mask = (uint64_t)msr_table[Index].read_mask; rsc_msr_tpl.write_mask = (uint64_t)msr_table[Index].write_mask; @@ -169,7 +168,6 @@ */ void add_resources_cmd(void) { - add_simple_resources(); add_msr_resources(); diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index cbb111a..2ca8673 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -157,7 +157,6 @@ } if (cpu == 0) { - // need to create the BIOS resource list once // first calculate the location in SMRAM addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index 98308b7..d4af667 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -107,13 +107,11 @@ const bool is_wake_error = !!(txt_ests & TXT_ESTS_WAKE_ERROR_STS); if (CONFIG(INTEL_TXT_LOGGING)) { - printk(BIOS_INFO, "TEE-TXT: TPM established: %s\n", establishment ? "true" : "false"); } if (establishment && is_wake_error) { - printk(BIOS_ERR, "TEE-TXT: Secrets remain in memory. SCLEAN is required.\n"); if (txt_ests & TXT_ESTS_TXT_RESET_STS) { -- To view, visit https://review.coreboot.org/c/coreboot/+/61553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90c5f175f3f407673f5b6573afc985b104e1fdd5 Gerrit-Change-Number: 61553 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Ethan Tsao, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61389/comment/1fe8a530_f6d00d33 PS11, Line 7: soc/intel/graphics: Create Kconfig for shifting graphic memory base > > Also, may be something like SOC_INTEL_GFX_GMADR_BEHIND_GTT could be your parent Kconfig which decides if we need such additional arithmetic or not. > > > > SOC_INTEL_GFX_MEMBASE_OFFSET can be dependent on parent Kconfig > > Seems unnecessary. With the `default 0x0`, the compiler will know what to do > (i.e. skip the arithmetic). Sure, SGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 17:21:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Nico Huber (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Ethan Tsao, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61389/comment/5af6afa7_b393d4b4 PS11, Line 7: soc/intel/graphics: Create Kconfig for shifting graphic memory base > Also, may be something like SOC_INTEL_GFX_GMADR_BEHIND_GTT could be your parent Kconfig which decides if we need such additional arithmetic or not. > > SOC_INTEL_GFX_MEMBASE_OFFSET can be dependent on parent Kconfig Seems unnecessary. With the `default 0x0`, the compiler will know what to do (i.e. skip the arithmetic). -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 17:00:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Werner Zeh, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61532 ) Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61532/comment/2dff77f6_693bed8d PS4, Line 10: align > nit: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Gerrit-Change-Number: 61532 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 16:55:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Werner Zeh, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Werner Zeh, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61532 to look at the new patch set (#5). Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ...................................................................... soc/intel/apollolake: Rename PWRMBASE macro and function This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is aligned with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() Additionally, make `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 --- M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c 6 files changed, 12 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61532/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Gerrit-Change-Number: 61532 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Don't override lpc_io_setup_comm_a_b()
by Angel Pons (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Sean Rhodes, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61552 ) Change subject: soc/intel/tigerlake: Don't override lpc_io_setup_comm_a_b() ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c28e8dcc1813740b2862b340c95bb80dab9d91e Gerrit-Change-Number: 61552 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 16:44:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Don't override lpc_io_setup_comm_a_b()
by Sean Rhodes (Code Review) 02 Feb '22

02 Feb '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61552 ) Change subject: soc/intel/tigerlake: Don't override lpc_io_setup_comm_a_b() ...................................................................... soc/intel/tigerlake: Don't override lpc_io_setup_comm_a_b() Move lpc_enable_fixed_io_ranges into the if statement so that it doesn't override what lpc_io_setup_comm_a_b() has done. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3c28e8dcc1813740b2862b340c95bb80dab9d91e --- M src/soc/intel/tigerlake/bootblock/pch.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61552/1 diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 7351492..7fcb103 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -119,15 +119,14 @@ if (config->lpc_ioe) { io_enables = config->lpc_ioe & lpc_ioe_enable_mask; + /* IO Decode Enable */ + lpc_enable_fixed_io_ranges(io_enables); } else { /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); } - /* IO Decode Enable */ - lpc_enable_fixed_io_ranges(io_enables); - /* Program generic IO Decode Range */ pch_enable_lpc(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c28e8dcc1813740b2862b340c95bb80dab9d91e Gerrit-Change-Number: 61552 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit February 2022