coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Lean Sheng Tan (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 4: (1 comment) File src/mainboard/intel/adlrvp/mainboard.c: https://review.coreboot.org/c/coreboot/+/61528/comment/df8dc2b1_8c485dd3 PS2, Line 70: const char *mainboard_vbt_filename(void) > WDYT? […] thanks Subrata. Done. but I wonder how chrome emerge handles multiple VBTs stitching, it would be nice to port it to coreboot and add multiple vbt support natively. -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 15:53:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Lean Sheng Tan (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons, Lean Sheng Tan. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61528 to look at the new patch set (#4). Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... mb/intel/adlrvp: Fix vbt loading error When booting ADL RVP, coreboot is unable to load VBT binary as makefile will rename VBT binary to "vbt.bin" when building coreboot.rom. The reason for having this function is that chromeOS has emerge tool to streamline the VBT stitching process to support multiple VBTs for different RVP boards; while we only need 1 vbt for generic non-chromeOS usage. Hence add a chomeos kconfig to guard this. TEST=Able to boot ADL RVP DDR5 with DP display. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 --- M src/mainboard/intel/adlrvp/mainboard.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/61528/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Lean Sheng Tan (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons, Lean Sheng Tan. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61528 to look at the new patch set (#3). Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... mb/intel/adlrvp: Fix vbt loading error When booting ADL RVP, coreboot is unable to load VBT binary as makefile will rename VBT binary to "vbt.bin" when building coreboot.rom. The reason for having this function is that chromeOS has emerge tool to streamline the VBT stitching process to support multiple VBTs for different RVP boards; while we only need 1 vbt for generic non-chromeOS usage. Hence add a chomeos kconfig to guard this. TEST=Able to boot ADL RVP DDR5 with DP display. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 --- M src/mainboard/intel/adlrvp/mainboard.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/61528/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 2: (1 comment) File src/mainboard/intel/adlrvp/mainboard.c: https://review.coreboot.org/c/coreboot/+/61528/comment/a863cf29_644fe3f1 PS2, Line 70: const char *mainboard_vbt_filename(void) WDYT? const char *mainboard_vbt_filename(void) { if (!CONFIG(CHROMEOS)) return "vbt.bin"; ..... } -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 15:45:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Don't pass unused PCIE_BASE option to UefiPayload
by Sean Rhodes (Code Review) 02 Feb '22

02 Feb '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61551 ) Change subject: payloads/tianocore: Don't pass unused PCIE_BASE option to UefiPayload ...................................................................... payloads/tianocore: Don't pass unused PCIE_BASE option to UefiPayload Remove passing PCIE_BASE to UefiPayloadPkg as it is unknown. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: If3f4a0f8d55610d9d545eac4d315bea11825fde0 --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/61551/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index f99b80e..d85111f 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -55,7 +55,7 @@ ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE else -BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G) +BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -D BOOTLOADER=COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(CBMEM) $(4G) endif all: clean build -- To view, visit https://review.coreboot.org/c/coreboot/+/61551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3f4a0f8d55610d9d545eac4d315bea11825fde0 Gerrit-Change-Number: 61551 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Lean Sheng Tan (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Christian Walter, Meera Ravindranath, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61528 to look at the new patch set (#2). Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... mb/intel/adlrvp: Fix vbt loading error When booting ADL RVP, coreboot is unable to load VBT binary as makefile will rename VBT binary to "vbt.bin" when building coreboot.rom. TEST=Able to boot ADL RVP DDR5 with DP display. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 --- M src/mainboard/intel/adlrvp/mainboard.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/61528/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Remove used build option
by Sean Rhodes (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Martin Roth, Stefan Reinauer. Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61550 ) Change subject: payloads/tianocore: Remove used build option ...................................................................... payloads/tianocore: Remove used build option Remove -DPS2_KEYBOARD_ENABLE being passed to edk2 as it has no effect. The correct argument for PS2 Keyboard is: -D PS2_KEYBOARD_ENABLE=TRUE -D SIO_BUS_ENABLE=TRUE This is hard coded into uefipayload_202107. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61550/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index a4ccfc7..f99b80e 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -9,7 +9,7 @@ project_git_branch=uefipayload_202107 upstream_git_repo=https://github.com/tianocore/edk2 -build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE +build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) project_git_branch=coreboot_fb -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Allow limiting writes to SMM via CMOS
by Sean Rhodes (Code Review) 02 Feb '22

02 Feb '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61549 ) Change subject: soc/intel: Allow limiting writes to SMM via CMOS ...................................................................... soc/intel: Allow limiting writes to SMM via CMOS Allow using CMOS setting of "smm_bwp" to limit writes, in addition to the Kconfig option. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ibd1078a843258b737fe55a491e2b0b285fcabb03 --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61549/1 diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 5ab0611..167dd02 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -66,7 +66,7 @@ fast_spi_set_bios_interface_lock_down(); /* Only allow writes in SMM */ - if (CONFIG(BOOTMEDIA_SMM_BWP)) { + if (CONFIG(BOOTMEDIA_SMM_BWP) || get_uint_option("smm_bwp", UINT_MAX)) { fast_spi_set_eiss(); fast_spi_enable_wp(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1078a843258b737fe55a491e2b0b285fcabb03 Gerrit-Change-Number: 61549 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/drivers/intel/i210: Remove unuseful 'return' in void function
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61548 ) Change subject: src/drivers/intel/i210: Remove unuseful 'return' in void function ...................................................................... src/drivers/intel/i210: Remove unuseful 'return' in void function Change-Id: Id33ef66e7388df2173ee8888265ed4379f05a93e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/i210/i210.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/61548/1 diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 32cae6f..8ecd3ec 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -203,7 +203,6 @@ } else { printk(BIOS_INFO, "I210: MAC address is up to date.\n"); } - return; } static void enable_bus_master(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/61548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id33ef66e7388df2173ee8888265ed4379f05a93e Gerrit-Change-Number: 61548 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/notify: Implement coreboot notify native driver
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Sridhar Siricilla, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60405 to look at the new patch set (#20). Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver ...................................................................... soc/intel/common/block/notify: Implement coreboot notify native driver This patch implements the required HECI operations to perform prior to booting to OS after platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects SOC_INTEL_COMMON_BLOCK_NOTIFY: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- A src/soc/intel/common/block/notify/Kconfig A src/soc/intel/common/block/notify/Makefile.inc A src/soc/intel/common/block/notify/notify.c 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 20 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2022