coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Nick Vaccaro (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Tim Wawrzynczak, Christian Walter, Werner Zeh, EricR Lai, Tim Chu. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 ) Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 18:20:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Nick Vaccaro (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Tim Wawrzynczak, Christian Walter, Werner Zeh, EricR Lai, Tim Chu. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 ) Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 18:20:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/notify: Implement coreboot notify native driver
by Sridhar Siricilla (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/common/block/notify/Kconfig: https://review.coreboot.org/c/coreboot/+/60405/comment/90ffd996_17ed42b0 PS21, Line 8: notification nit: notification operations mean? -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 21 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 18:17:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/notify: Implement coreboot notify native driver
by Sridhar Siricilla (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver ...................................................................... Patch Set 21: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60405/comment/ceff4fce_fc863f9a PS19, Line 7: soc/intel/common/block/notify: Implement coreboot notify native driver > Here is my motivation apart from what Arthur, Angel and Sheng had mentioned. […] Thanks for views.. my worry part is, if you switch off the FSP Notify code, and enables coreboot native code in this regard, then we might end-up loose changes if SOC team adds in the FSP notify API though the changes are optional. My concern is with respect to maintenance. -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 21 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 18:14:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/designware/dw_i2c: use cb_err for dw_i2c_gen_speed_config
by Felix Held (Code Review) 02 Feb '22

02 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61512 ) Change subject: drivers/i2c/designware/dw_i2c: use cb_err for dw_i2c_gen_speed_config ...................................................................... drivers/i2c/designware/dw_i2c: use cb_err for dw_i2c_gen_speed_config Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8d96e5f72a8b3552ab39c1d298bafcc224bf9e55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61512 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/i2c/designware/dw_i2c.c M src/drivers/i2c/designware/dw_i2c.h 2 files changed, 6 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index bfb5971..2a7c6fc 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -615,7 +615,7 @@ return CB_SUCCESS; } -int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, +enum cb_err dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, enum i2c_speed speed, const struct dw_i2c_bus_config *bcfg, struct dw_i2c_speed_config *config) @@ -634,12 +634,11 @@ if (bcfg->speed_config[i].speed != speed) continue; memcpy(config, &bcfg->speed_config[i], sizeof(*config)); - return 0; + return CB_SUCCESS; } /* Use the time calculation. */ - return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg, ic_clk, config) == - CB_SUCCESS ? 0 : -1; + return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg, ic_clk, config); } static enum cb_err dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, @@ -669,7 +668,7 @@ } /* Generate speed config based on clock */ - if (dw_i2c_gen_speed_config((uintptr_t)regs, speed, bcfg, &config) < 0) + if (dw_i2c_gen_speed_config((uintptr_t)regs, speed, bcfg, &config) != CB_SUCCESS) return CB_ERR; /* Select this speed in the control register */ @@ -830,7 +829,7 @@ /* Report currently used timing values for the OS driver */ acpigen_write_scope(path); - if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) >= 0) { + if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) == CB_SUCCESS) { dw_i2c_acpi_write_speed_config(&sgen); } /* Now check if there are more speed settings available and report them as well. */ diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 3d8e663..464facf 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -100,11 +100,8 @@ /* * Generate speed config based on clock - * Return value: - * -1 = failure - * 0 = success */ -int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, +enum cb_err dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, enum i2c_speed speed, const struct dw_i2c_bus_config *bcfg, struct dw_i2c_speed_config *config); -- To view, visit https://review.coreboot.org/c/coreboot/+/61512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d96e5f72a8b3552ab39c1d298bafcc224bf9e55 Gerrit-Change-Number: 61512 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Tim Wawrzynczak (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Wonkyu Kim, Ravishankar Sarawadi, Paul Menzel, Raj Astekar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61389/comment/c177d5d9_36df1c38 PS11, Line 9: create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to : shift graphic memory base if require. 72 characters wide please https://review.coreboot.org/c/coreboot/+/61389/comment/351678a2_9e0fa5a4 PS11, Line 10: require `required` -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 18:01:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Ethan Tsao (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Ethan Tsao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/61389/comment/18d0d333_48e99e81 PS11, Line 122: printk(BIOS_INFO, "gfx memory bar(0x18) = 0x%lx GFX_MEMBASE_OFFSET = 0x%x\n", : memory_base, CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET); > do we need this ? The purpose of this message is to print gfx basic information without adding debug message and re-build while there is gfx issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 18:00:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers: Get rid of unnecessary blank lines {before,after} blace
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61557 ) Change subject: src/drivers: Get rid of unnecessary blank lines {before,after} blace ...................................................................... src/drivers: Get rid of unnecessary blank lines {before,after} blace Change-Id: Ic1b38e93d919c1286a8d130700a4a2bfd6b55258 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/heapmanager.c M src/drivers/amd/agesa/state_machine.c M src/drivers/aspeed/common/ast_dp501.c M src/drivers/aspeed/common/ast_mode.c M src/drivers/aspeed/common/ast_post.c M src/drivers/crb/tis.c M src/drivers/crb/tpm.c M src/drivers/generic/max98357a/chip.h M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/ww_ring/ww_ring.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/header_display.c M src/drivers/intel/gma/opregion.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/ipmi/ipmi_fru.c M src/drivers/net/ne2k.c M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/smmstore/store.c M src/drivers/spi/tpm/tis.c M src/drivers/tpm/ppi.c M src/drivers/usb/ehci.h 22 files changed, 1 insertion(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61557/1 diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index c1fac0d..2910c9d 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -346,7 +346,6 @@ AllocParams->BufferLength = AllocNodePtr->BufferSize; return AGESA_SUCCESS; - } AGESA_STATUS HeapManagerCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr) diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 31db0b6..ef33cc5 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -159,7 +159,6 @@ { break; } - } return status; } @@ -222,7 +221,6 @@ { break; } - } return status; } diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 924ca57..ba0833c 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -146,7 +146,6 @@ data = ast_mindwm(ast, 0x1e6e2100) & 0x01; if (!data) { - if (ast->dp501_fw_addr) { fw_addr = ast->dp501_fw_addr; len = 32*1024; diff --git a/src/drivers/aspeed/common/ast_mode.c b/src/drivers/aspeed/common/ast_mode.c index e5832e7..3ab91c2 100644 --- a/src/drivers/aspeed/common/ast_mode.c +++ b/src/drivers/aspeed/common/ast_mode.c @@ -26,7 +26,6 @@ /* FIXME: Gamma cor 2.6 ? */ for (int i = 0; i < 256; i++) ast_load_palette_index(ast, i, i, i, i); - } static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index e644d91..08bc42c 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -788,8 +788,8 @@ } reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23); ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); - } + static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) { u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0; @@ -1085,7 +1085,6 @@ param->dram_config |= 0x0c; break; } - } static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param) @@ -1226,7 +1225,6 @@ ast_moutdwm(ast, 0x1E6E0050, 0x80000000); ast_moutdwm(ast, 0x1E6E0050, 0x00000000); #endif - } static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param) @@ -1617,7 +1615,6 @@ ast_moutdwm(ast, 0x1E6E0050, 0x80000000); ast_moutdwm(ast, 0x1E6E0050, 0x00000000); #endif - } static void ast_post_chip_2300(struct drm_device *dev) @@ -1883,7 +1880,6 @@ static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table) { - ast_moutdwm(ast, 0x1E6E0004, 0x00000303); ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 800d145..dc61c1e 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -51,7 +51,6 @@ int tis_close(void) { if (tpm_is_open) { - /* * Do we need to do something here, like waiting for a * transaction to stop? diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index 9c8f249..1bdca00 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -110,7 +110,6 @@ */ static uint8_t crb_activate_locality(void) { - uint8_t locality = (read8(CRB_REG(0, CRB_REG_LOC_STATE)) >> 2) & 0x07; printk(BIOS_SPEW, "Active locality: %i\n", locality); @@ -174,7 +173,6 @@ */ int tpm2_init(void) { - if (crb_probe()) { printk(BIOS_ERR, "TPM: Probe failed.\n"); return -1; diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h index 1c4aa3d..66ebecf 100644 --- a/src/drivers/generic/max98357a/chip.h +++ b/src/drivers/generic/max98357a/chip.h @@ -3,7 +3,6 @@ #include <acpi/acpi_device.h> struct drivers_generic_max98357a_config { - /* ACPI _HID */ const char *hid; diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index b96099c..840b947 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -346,7 +346,6 @@ burstcnt); if (rc == 0) size += burstcnt; - } return size; } diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index 19aa6da..98c162b 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -375,7 +375,6 @@ for (i = 0, ledc = lp55231s; i < WW_RING_NUM_LED_CONTROLLERS; i++, ledc++) { - ledc->i2c_bus = i2c_bus; ledc->dev_addr = LP55231_I2C_BASE_ADDR + i; diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 5d41a01..fc05b91 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -19,7 +19,6 @@ * with different TSEG size configurations. */ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); - } /* This is the romstage entry called from cpu/intel/car/romstage.c */ diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index fd8316e..386708f 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -129,7 +129,6 @@ for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { - if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) continue; @@ -193,7 +192,6 @@ for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { - if (hob->type != HOB_TYPE_GUID_EXTENSION) continue; diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index 4c8085e..3241856 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -44,5 +44,4 @@ printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", (size_t)hdr->notify_phase_entry_offset); } - } diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 430bda3..63e248c 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -290,7 +290,6 @@ static void opregion_add_ext_vbt(igd_opregion_t *opregion, uint8_t *ext_vbt, optionrom_vbt_t *vbt) { - opregion_header_t *header = &opregion->header; /* Copy VBT into extended VBT region (at offset 8 KiB) */ memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 4e4a92c..7220f27 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -356,7 +356,6 @@ acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) { - if (!config->dfp[dfp_port].power_gpio.pin_count) { printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n", __func__, dfp_port, dev_path(dev)); diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index d26a9b7..822e5bf 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -571,5 +571,4 @@ printk(BIOS_DEBUG, "chassis custom data %i: %s\n", count, *(chassis_info.chassis_custom + count)); } - } diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 83d4ccf..235c909 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -124,7 +124,6 @@ int acc = 0; do { - c = str[i]; if ((c >= '0') && (c <= '9')) { acc *= 16; diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index fd659f1..f45a3a0 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -267,7 +267,6 @@ /* If we are in normal mode set the boot count to 0 */ if (byte & RTC_BOOT_NORMAL) byte &= 0x0f; - } outb(byte, RTC_PORT(1)); diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 24e8a88..9d19a7c 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -161,7 +161,6 @@ return CB_ERR; return CB_SUCCESS; - } /* * Append data to region diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 6465b40..da4c1a8 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -40,7 +40,6 @@ int tis_close(void) { if (tpm_is_open) { - /* * Do we need to do something here, like waiting for a * transaction to stop? diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c index 6b02d45..6183e3b 100644 --- a/src/drivers/tpm/ppi.c +++ b/src/drivers/tpm/ppi.c @@ -582,7 +582,6 @@ found = true; } } else { - for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { ppib->func[tpm2_funcs[i]] = 1; if (ppib->pprq == tpm2_funcs[i]) diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index 9635460..b9054cf 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -42,7 +42,6 @@ /* Section 2.3 Host Controller Operational Registers */ struct ehci_regs { - /* USBCMD: offset 0x00 */ u32 command; -- To view, visit https://review.coreboot.org/c/coreboot/+/61557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1b38e93d919c1286a8d130700a4a2bfd6b55258 Gerrit-Change-Number: 61557 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Ethan Tsao (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Ethan Tsao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/61389/comment/92db8203_ebc82865 PS11, Line 129: memory_base = memory_base + CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET; > memory_base += CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET; […] I think the purpose of if clause is checking if memory bar is zero. If we move this line above 'if clause', then we cannot catch "memory bar = 0" when CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET is not zero. -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 17:57:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Raul Rangel (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Kangheui Won. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h: https://review.coreboot.org/c/coreboot/+/61368/comment/81a08b9c_b1c73f19 PS4, Line 145: NON_CHROME_BOOK_BOOT_MODE = 0x0, : CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, : CHROME_BOOK_BOOT_MODE_PRODUCTION = 0x2, : CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, : CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check > AMD releases PSP binary to Google with syscall headers. […] I didn't think coreboot style applied to VC. -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 17:42:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2022