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Hello build bot (Jenkins), Lee Leahy, Christian Walter, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61557
to look at the new patch set (#2).
Change subject: drivers: Get rid of unnecessary blank lines {before,after} brace
......................................................................
drivers: Get rid of unnecessary blank lines {before,after} brace
Change-Id: Ic1b38e93d919c1286a8d130700a4a2bfd6b55258
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/drivers/amd/agesa/heapmanager.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/aspeed/common/ast_dp501.c
M src/drivers/aspeed/common/ast_mode.c
M src/drivers/aspeed/common/ast_post.c
M src/drivers/crb/tis.c
M src/drivers/crb/tpm.c
M src/drivers/generic/max98357a/chip.h
M src/drivers/i2c/tpm/tpm.c
M src/drivers/i2c/ww_ring/ww_ring.c
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/header_display.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/usb4/retimer/retimer.c
M src/drivers/ipmi/ipmi_fru.c
M src/drivers/net/ne2k.c
M src/drivers/pc80/rtc/mc146818rtc.c
M src/drivers/smmstore/store.c
M src/drivers/spi/tpm/tis.c
M src/drivers/tpm/ppi.c
M src/drivers/usb/ehci.h
22 files changed, 1 insertion(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61557/2
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Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
Patch Set 21:
(1 comment)
File src/soc/intel/common/block/notify/Kconfig:
https://review.coreboot.org/c/coreboot/+/60405/comment/d2d9a14b_cd13d9eb
PS21, Line 8: notification
> I need to rephrase this for sure, but just to answer your question. […]
Yes, it needs rephrasing, coreboot need not mimic FSP API when coreboot implements alternate flow.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61557 )
Change subject: src/drivers: Get rid of unnecessary blank lines {before,after} blace
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61557/comment/178858cc_c53ea4eb
PS1, Line 7: blace
brace
https://review.coreboot.org/c/coreboot/+/61557/comment/bb5b5d9d_47cfa262
PS1, Line 7: src/drivers
drivers
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Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61558 )
Change subject: soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section. The EFS FMAP
partition is checked to ensure it begins at the expected location.
Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/Makefile.inc
A src/soc/amd/common/block/psp/efs_fmap_check.c
3 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61558/1
diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig
index c5ec560..7ef7e40 100644
--- a/src/soc/amd/common/block/psp/Kconfig
+++ b/src/soc/amd/common/block/psp/Kconfig
@@ -27,3 +27,11 @@
and each mainboard can choose to select an appropriate fanless or
fanned set of blobs. Ask your AMD representative whether your APU
is considered fanless.
+
+config AMD_SOC_SEPARATE_EFS_SECTION
+ bool
+ help
+ Use separate EFS FMAP section instead of putting EFS into CBFS. The
+ FMAP section must begin exactly at the location the EFS needs to be
+ placed in the flash. This option can be used to place the EFS right
+ after the 128kByte EC firmware at the beginning of the flash.
diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc
index 94dc57c..5bae663 100644
--- a/src/soc/amd/common/block/psp/Makefile.inc
+++ b/src/soc/amd/common/block/psp/Makefile.inc
@@ -6,6 +6,7 @@
smm-y += psp_smm.c
bootblock-y += psp_efs.c
+bootblock-$(CONFIG_AMD_SOC_SEPARATE_EFS_SECTION) += efs_fmap_check.c
verstage-y += psp_efs.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP
diff --git a/src/soc/amd/common/block/psp/efs_fmap_check.c b/src/soc/amd/common/block/psp/efs_fmap_check.c
new file mode 100644
index 0000000..88a0bb4
--- /dev/null
+++ b/src/soc/amd/common/block/psp/efs_fmap_check.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/psp_efs.h>
+#include <assert.h>
+#include <fmap_config.h>
+
+#define FMAP_EFS_OFFSET (FMAP_SECTION_EFS_START - FMAP_SECTION_FLASH_START)
+
+_Static_assert(FMAP_EFS_OFFSET == EFS_OFFSET, "FMAP EFS Offset does not match "
+ "EFS Offset - check your config");
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61369 )
Change subject: psp_verstage: report developer mode to PSP
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
this likely needs to be ported forward to sabrina; from what i've seen without that being ported forward a verstage on psp build for soc/amd/sabrina will fail
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Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
Patch Set 21:
(1 comment)
File src/soc/intel/common/block/notify/Kconfig:
https://review.coreboot.org/c/coreboot/+/60405/comment/c6df8001_ec96f4e8
PS21, Line 8: notification
> nit: notification operations mean?
I need to rephrase this for sure, but just to answer your question.
Notification to certain IPs about
- Time to go to low power mode
- Let me lock your memory range
- Let me hide you from OS if needed etc.
In any bootloader, we typically have two phases
1. Where bootloader initialise a hardware block and ask to perform some operation.
2. Prior loading paylaod/OS, it also decides if we need to perform any housekeeping task for those IP prior to load paylaod/os.
when I have written "notification", I meant the #2 task.
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Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
Patch Set 21:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60405/comment/2ebe1a03_afd495e2
PS19, Line 7: soc/intel/common/block/notify: Implement coreboot notify native driver
> Thanks for views.. my worry part is, if you switch off the FSP Notify code, and enables coreboot native code in this regard, then we might end-up loose changes if SOC team adds in the FSP notify API though the changes are optional. My concern is with respect to maintenance.
Valid concern and we can have few strategies to ensure robustness
1. Refer to the SoC platform FAS security chapter and implement those recommended programming (ideally those are meant for OEM/ODM to implement, all IBVs do refer to the same document).
2. Intel can own this piece like what is being done YoY for Cache-as-RAM native code in `soc/intel/common/block/cpu/car`, eNEM as replacement for FSP-T for each SoC program. (on ADL it took several months to validate eNEM and enable finally) In the past we didn't pick FSP-T just to avoid extra enabling time for CAR/eNEM, right?
Please share your thoughts on this.
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Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
......................................................................
Patch Set 5: Code-Review+1
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