coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Use PMC IPC to disable HECI1
by EricR Lai (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61458 ) Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1 ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Gerrit-Change-Number: 61458 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:34:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Use PMC IPC to disable HECI1
by EricR Lai (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61458 ) Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1 ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/61458/comment/a2732a18_fc73112f PS7, Line 81: select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT > Yup, this basically defines the relation between wish to disable HECI1 and what interface to use. […] I am fine :p -- To view, visit https://review.coreboot.org/c/coreboot/+/61458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Gerrit-Change-Number: 61458 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:34:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Maulik V Vaghela, Christian Walter, Angel Pons, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I agree The fallback path is still "vbt.bin" ? Do we have issue. return "vbt.bin"; I guess the issue here is based on DDR5 board id, we are expecting to stitch a vbt_adlrvp_ddr5.bin instead vbt.bin case ADL_P_DDR5_1: case ADL_P_DDR5_2: return "vbt_adlrvp_ddr5.bin"; -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:33:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Maulik V Vaghela, Christian Walter, Angel Pons, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > My suggestion is can we check if that vbt file exists in CBFS else fallback to vbt.bin?? […] I agree -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:31:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 ) Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/61519/comment/f81c9fc6_cbab54e0 PS4, Line 199: : if (eop_sent) { : printk(BIOS_ERR, "EOP already sent\n"); : return; : } : > I suggested adding this as there was a TODO comment, and I thought this would be better than nothing. However, if there's something better, let's use it instead. I have raised a bug b/217483219 to get feedback from Intel. Will share the progress. From timing standpoint what we wish to do. Need suggestion: 1. Keep TODO and go ahead. 2. Have Static variable and go head 3. Wait for Intel (b/217483219) to share a possible path -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:30:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Meera Ravindranath (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Christian Walter, Angel Pons, Lean Sheng Tan. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: So the very reason, we came up with this part of code was to handle multiple vbt configurations of different rvp boards. Having a single vbt was not a feasible solution. If we remove this now, how will we handle the other vbt files? -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:25:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Maulik V Vaghela (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Christian Walter, Meera Ravindranath, Angel Pons, Lean Sheng Tan. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: My suggestion is can we check if that vbt file exists in CBFS else fallback to vbt.bin?? Get vbt_file_name from the mainboard..In case file doesn't exist, fallback to vbt.bin as a default. What do you think @Subrata @Sheng? -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:23:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Maulik V Vaghela (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Christian Walter, Meera Ravindranath, Angel Pons, Lean Sheng Tan. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Isn't this function being added to ensure we have single binary with different vbt configuration. […] Yes Subrata..this function was added to ensure that we use different VBT binaries based on SKU ID. I think current issue is all binary must be stitched into coreboot to get this function working else it might throw and error. so when someone wants to just stitch only vbt.bin, they may need this patch to make it work -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 07:22:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Use SBI msg to disable HECI1
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61453 ) Change subject: soc/intel/elkhartlake: Use SBI msg to disable HECI1 ...................................................................... soc/intel/elkhartlake: Use SBI msg to disable HECI1 Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61453 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7f8bca0..a8d7618 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -46,6 +46,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Gerrit-Change-Number: 61453 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse: Rework heci_disable function
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61431 ) Change subject: soc/intel/common/cse: Rework heci_disable function ...................................................................... soc/intel/common/cse: Rework heci_disable function This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/alderlake/smihandler.c M src/soc/intel/apollolake/include/soc/pcr_ids.h M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/elkhartlake/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/tigerlake/smihandler.c M src/soc/intel/xeon_sp/include/soc/pcr_ids.h 13 files changed, 78 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index d9ea96a..61fecdf 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -20,7 +20,7 @@ return; if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci_disable(); + heci1_disable(); } int smihandler_soc_disable_busmaster(pci_devfn_t dev) diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 4e043bb..b81d700 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -27,5 +27,6 @@ #define PID_PSF3 0xC6 #define PID_DMI 0x00 /* Reserved */ +#define PID_CSME0 0x9A /* Reserved */ #endif /* SOC_INTEL_APL_PCR_H */ diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 61283c9..ac25990 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -17,7 +17,7 @@ void smihandler_soc_at_finalize(void) { if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) - heci_disable(); + heci1_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 23e08e6..1a112bd6 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -14,13 +14,32 @@ Mainboard users to select this config to make HECI1 `function disable` prior to handing off to payload. -config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM +config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI bool default y if HECI_DISABLE_USING_SMM select SOC_INTEL_COMMON_BLOCK_P2SB help - Use this config to include common CSE block to make HECI function - disable in SMM mode + Use this config to allow common CSE block to make HECI1 function disable + in the SMM mode. From CNL PCH onwards,`HECI1` disabling can only be done + using the non-posted sideband write after FSP-S sets the postboot_sai + attribute. + +config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC + bool + default n + select SOC_INTEL_COMMON_BLOCK_PMC + help + Use this config to allow common CSE block to make HECI1 function disable + using PMC IPC command `0xA9`. From TGL PCH onwards, disabling heci1 + device using PMC IPC doesn't required to run the operation in SMM. + +config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR + bool + default n + select SOC_INTEL_COMMON_BLOCK_PCR + help + Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) + to make `HECI1` device disable using private configuration register (PCR) write. config SOC_INTEL_CSE_LITE_SKU bool diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 0e5dcda..11a4891 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -2,7 +2,8 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c -smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 1256fd1..ab8b3ad 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <commonlib/helpers.h> #include <console/console.h> #include <device/pci.h> @@ -15,8 +17,20 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 +/* Disable HECI using PCR */ +static void heci1_disable_using_pcr(void) +{ + soc_disable_heci1_using_pcr(); +} + +/* Disable HECI using PMC IPC communication */ +static void heci1_disable_using_pmc(void) +{ + cse_disable_mei_devices(); +} + /* Disable HECI using Sideband interface communication */ -void heci_disable(void) +static void heci1_disable_using_sbi(void) { struct pcr_sbi_msg msg = { .pid = PID_CSME0, @@ -46,3 +60,23 @@ /* hide p2sb device */ p2sb_hide(); } + +void heci1_disable(void) +{ + if (!CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + return; + + if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI)) { + printk(BIOS_INFO, "Disabling Heci using SBI in SMM mode\n"); + return heci1_disable_using_sbi(); + } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) { + printk(BIOS_INFO, "Disabling Heci using PMC IPC\n"); + return heci1_disable_using_pmc(); + } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR)) { + printk(BIOS_INFO, "Disabling Heci using PCR\n"); + return heci1_disable_using_pcr(); + } else { + printk(BIOS_ERR, "%s Error: Unable to make HECI1 function disable!\n", + __func__); + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 9bf35da..15b7313 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -311,8 +311,8 @@ * Returns 0 on failure and 1 on success. */ int heci_reset(void); -/* Disable HECI using Sideband interface communication */ -void heci_disable(void); +/* Disable HECI1 using Sideband interface communication */ +void heci1_disable(void); /* Reads config value from a specified offset in the CSE PCI Config space. */ uint32_t me_read_config32(int offset); @@ -489,4 +489,12 @@ /* Function to make cse disable using PMC IPC */ bool cse_disable_mei_devices(void); +/* + * SoC override API to make heci1 disable using PCR. + * + * Allow SoC to implement heci1 disable override due to PSF registers being + * different across SoC generation. + */ +void soc_disable_heci1_using_pcr(void); + #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c index e3c5012..eb5a576 100644 --- a/src/soc/intel/elkhartlake/smihandler.c +++ b/src/soc/intel/elkhartlake/smihandler.c @@ -17,7 +17,7 @@ void smihandler_soc_at_finalize(void) { if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci_disable(); + heci1_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5fb4f43..7958da6 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -17,7 +17,7 @@ void smihandler_soc_at_finalize(void) { if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci_disable(); + heci1_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 4639676..3dca4a2 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -17,7 +17,7 @@ void smihandler_soc_at_finalize(void) { if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) - heci_disable(); + heci1_disable(); } int smihandler_soc_disable_busmaster(pci_devfn_t dev) diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index b9e2cb9..84587a8 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -7,6 +7,7 @@ * Port ids */ #define PID_PSTH 0x89 +#define PID_CSME0 0x90 #define PID_GPIOCOM3 0xAC #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 8e343c3..843733f 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -17,7 +17,7 @@ void smihandler_soc_at_finalize(void) { if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) - heci_disable(); + heci1_disable(); } int smihandler_soc_disable_busmaster(pci_devfn_t dev) diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index 6ba9609..8c0b669 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -3,6 +3,7 @@ #ifndef _PCR_IDS_H_ #define _PCR_IDS_H_ +#define PID_CSME0 0x90 #define PID_ITSS 0xC4 #define PID_RTC 0xC3 #define PID_DMI 0xEF 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Gerrit-Change-Number: 61431 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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coreboot-gerrit February 2022