coreboot-gerrit February 2022

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Change in coreboot[master]: util/spd_tools/spd_gen: Add support for Sabrina SoC
by Karthik Ramasubramanian (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Reka Norman. Hello Reka Norman, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61542 to look at the new patch set (#2). Change subject: util/spd_tools/spd_gen: Add support for Sabrina SoC ...................................................................... util/spd_tools/spd_gen: Add support for Sabrina SoC Add support to generate SPD binary for Sabrina SoC. Mainboards using Sabrina SoC are planning to use LP5 memory technology. Some of the SPD bytes expected by Sabrina differ from the existing ADL. To start with, memory training code for Sabrina expects SPD Revision 1.1. More patches will follow to accommodate additional differences. BUG=b:211510456 TEST=make -C util/spd_tools. Generate SPD binaries for the existing memory parts in lp5/memory_parts.json and observe that SPDs for Sabrina is generated as a separate set without impacting the ADL mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df --- M util/spd_tools/src/spd_gen/lp5.go M util/spd_tools/src/spd_gen/spd_gen.go 2 files changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/61542/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df Gerrit-Change-Number: 61542 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: spd/lp5: Generate initial SPDs for Sabrina SoC
by Karthik Ramasubramanian (Code Review) 02 Feb '22

02 Feb '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61543 ) Change subject: spd/lp5: Generate initial SPDs for Sabrina SoC ...................................................................... spd/lp5: Generate initial SPDs for Sabrina SoC Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 --- M spd/lp5/platforms_manifest.generated.txt A spd/lp5/set-1/parts_spd_manifest.generated.txt A spd/lp5/set-1/spd-1.hex A spd/lp5/set-1/spd-2.hex A spd/lp5/set-1/spd-empty.hex 5 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/61543/1 diff --git a/spd/lp5/platforms_manifest.generated.txt b/spd/lp5/platforms_manifest.generated.txt index 95f5dbb..356c99aa 100644 --- a/spd/lp5/platforms_manifest.generated.txt +++ b/spd/lp5/platforms_manifest.generated.txt @@ -2,3 +2,4 @@ # util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 ADL,set-0 +SBR,set-1 diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt new file mode 100644 index 0000000..31a729d --- /dev/null +++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt @@ -0,0 +1,6 @@ +# Generated by: +# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 + +MT62F512M32D2DR-031 WT:B,spd-1.hex +MT62F1G32D4DR-031 WT:B,spd-2.hex +H9JCNNNCP3MLYR-N6E,spd-2.hex diff --git a/spd/lp5/set-1/spd-1.hex b/spd/lp5/set-1/spd-1.hex new file mode 100644 index 0000000..6ae3d79 --- /dev/null +++ b/spd/lp5/set-1/spd-1.hex @@ -0,0 +1,32 @@ +23 11 13 0E 15 1A 95 08 00 00 00 00 02 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-2.hex b/spd/lp5/set-1/spd-2.hex new file mode 100644 index 0000000..876d40c --- /dev/null +++ b/spd/lp5/set-1/spd-2.hex @@ -0,0 +1,32 @@ +23 11 13 0E 15 1A B5 08 00 00 00 00 0A 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-empty.hex b/spd/lp5/set-1/spd-empty.hex new file mode 100644 index 0000000..1a5be53 --- /dev/null +++ b/spd/lp5/set-1/spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/61543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Gerrit-Change-Number: 61543 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/spd_tools/spd_gen: Add support for Sabrina SoC
by Karthik Ramasubramanian (Code Review) 02 Feb '22

02 Feb '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61542 ) Change subject: util/spd_tools/spd_gen: Add support for Sabrina SoC ...................................................................... util/spd_tools/spd_gen: Add support for Sabrina SoC Add support to generate SPD binary for Sabrina SoC. Mainboards using Sabrina SoC are planning to use LP5 memory technology. Some of the SPD bytes expected by Sabrina differ from the existing ADL. To start with, memory training code for Sabrina expects SPD Revision 1.1. More patches will follow to accommodate additional differences. BUG=b:211510456 TEST=make -C util/spd_tools. Generate SPD binaries for the existing memory parts in lp5/memory_parts.json and observe that SPDs for Sabrina is generated as a separate set without impacting the ADL mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df --- M util/spd_tools/src/spd_gen/lp5.go M util/spd_tools/src/spd_gen/spd_gen.go 2 files changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/61542/1 diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go index 2e52bd5..db8c829 100644 --- a/util/spd_tools/src/spd_gen/lp5.go +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -55,6 +55,10 @@ getVal LP5SPDAttribFunc } +type LP5Set struct { + SPDRevision byte +} + /* ------------------------------------------------------------------------------------------ */ /* Constants */ /* ------------------------------------------------------------------------------------------ */ @@ -100,9 +104,13 @@ LP5SPDValueSize = 0x23 /* - * Revision 1.0. + * Revision 1.0. Expected by ADL */ - LP5SPDValueRevision = 0x10 + LP5SPDValueRevision1_0 = 0x10 + /* + * Revision 1.1. Expected by Sabrina + */ + LP5SPDValueRevision1_1 = 0x11 /* * As per advisory #616599, ADL MRC expects LPDDR5 memory type = 0x13. @@ -177,6 +185,16 @@ var LP5PlatformSetMap = map[int][]int{ 0: {PlatformADL}, + 1: {PlatformSBR}, +} + +var LP5SetInfo = map[int]LP5Set{ + 0: { + SPDRevision: LP5SPDValueRevision1_0, + }, + 1: { + SPDRevision: LP5SPDValueRevision1_1, + }, } var LP5PartAttributeMap = map[string]LP5MemAttributes{} @@ -280,7 +298,7 @@ var LP5SPDAttribTable = map[int]LP5SPDAttribTableEntry{ LP5SPDIndexSize: {constVal: LP5SPDValueSize}, - LP5SPDIndexRevision: {constVal: LP5SPDValueRevision}, + LP5SPDIndexRevision: {getVal: LP5EncodeSPDRevision}, LP5SPDIndexMemoryType: {constVal: LP5SPDValueMemoryType}, LP5SPDIndexModuleType: {constVal: LP5SPDValueModuleType}, LP5SPDIndexDensityBanks: {getVal: LP5EncodeDensityBanks}, @@ -309,6 +327,16 @@ /* ------------------------------------------------------------------------------------------ */ /* Functions */ /* ------------------------------------------------------------------------------------------ */ +func LP5EncodeSPDRevision(memAttribs *LP5MemAttributes) byte { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false { + return 0 + } + + return f.SPDRevision + +} func LP5EncodeDensityBanks(memAttribs *LP5MemAttributes) byte { var b byte diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go index 6cc9102..9e939f0 100644 --- a/util/spd_tools/src/spd_gen/spd_gen.go +++ b/util/spd_tools/src/spd_gen/spd_gen.go @@ -72,6 +72,7 @@ PlatformJSL PlatformPCO PlatformCZN + PlatformSBR PlatformMax ) @@ -90,6 +91,7 @@ PlatformJSL: "JSL", PlatformPCO: "PCO", PlatformCZN: "CZN", + PlatformSBR: "SBR", } var memTechMap = map[string]memTech{ -- To view, visit https://review.coreboot.org/c/coreboot/+/61542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df Gerrit-Change-Number: 61542 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/notify: Implement coreboot notify native driver
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Sridhar Siricilla, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver ...................................................................... Patch Set 19: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60405/comment/5cd8bf8c_e7820006 PS19, Line 7: soc/intel/common/block/notify: Implement coreboot notify native driver > And getting fixes in coreboot code is generally faster than getting fixes in FSP ^^ Here is my motivation apart from what Arthur, Angel and Sheng had mentioned. 1. Boot time impact, sending EOP from FSP takes ~35ms on all Intel platforms (I have worked between SKL till ADL) until we had to refactor the code into coreboot and implement the logic wisely understanding the timing impact, it took ~3ms. 2. Reduce the closed source binaries and specifically the optional one. Do you know one can boot to an OS even after skip calling FSP-S and onwards all APIs (including FSP APIs)? What is the downside of this design? Missing SoC recommended chipset programming. These patch sets would like to bring those recommended programming (as documented in EDS/FAS) in open-source coreboot so we know what is the downside. 3. Maintenance on ADL, after UPD refactoring, FSP missed sending EOP (as default was sending EOP from DXE). Who will debug such an issue and tap on FSP UPD. Having code in coreboot would help more eyes to catch such issues and reduce YoY maintenance. 4. Leveraging more common code, all code being implemented as part of these patch sets are just leveraging existing IA common code libraries effectively without crossing any border between FSP close source and coreboot open source. We were enough motivated in past to make the FSP-T optional and we would like to empower coreboot in more possible ways. If your concern is redundancy then there are always ways to fix that, isn’t it. -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 19 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 04:57:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Fix choice X2APIC_ONLY
by Kyösti Mälkki (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Nico Huber, Wonkyu Kim, Angel Pons, Kyösti Mälkki. Hello build bot (Jenkins), Nico Huber, Wonkyu Kim, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60213 to look at the new patch set (#4). Change subject: cpu/x86/lapic: Fix choice X2APIC_ONLY ...................................................................... cpu/x86/lapic: Fix choice X2APIC_ONLY When sending self an IPI, some instructions may be processed before IPI is serviced. Spend some time doing nothing, to avoid entering a printk() and acquiring console_lock and dead-locking. Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/x86/lapic.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/60213/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb Gerrit-Change-Number: 60213 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/lapic: Move LAPIC configuration to MP init
by Kyösti Mälkki (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Christian Walter, Tim Wawrzynczak, Vanessa Eusebio, Michal Motyl, Felix Held, Tim Chu. Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Christian Walter, Tim Wawrzynczak, Vanessa Eusebio, Michal Motyl, Felix Held, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58387 to look at the new patch set (#7). Change subject: cpu/x86/lapic: Move LAPIC configuration to MP init ...................................................................... cpu/x86/lapic: Move LAPIC configuration to MP init Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/common/common_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_65x/model_65x_init.c M src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/model_68x/model_68x_init.c M src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/model_6xx/model_6xx_init.c M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/model_f4x_init.c M src/cpu/qemu-x86/qemu.c M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/cpu.c 42 files changed, 12 insertions(+), 143 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58387/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Gerrit-Change-Number: 58387 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Damien Zammit, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Damien Zammit, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55413 to look at the new patch set (#9). Change subject: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER ...................................................................... cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER Leftover from using UDELAY_LAPIC on these platforms. Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c 7 files changed, 0 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/55413/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/55413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Gerrit-Change-Number: 55413 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/lapic: Add lapic_send_ipi_self,others()
by Kyösti Mälkki (Code Review) 02 Feb '22

02 Feb '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60713 to look at the new patch set (#2). Change subject: cpu/x86/lapic: Add lapic_send_ipi_self,others() ...................................................................... cpu/x86/lapic: Add lapic_send_ipi_self,others() This avoids unnecessary passing of APIC ID parameter and allows some minor optimisation for X2APIC mode. Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_stop.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h 3 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/60713/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5 Gerrit-Change-Number: 60713 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Felix Singer, Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61541 ) Change subject: mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2 ...................................................................... Patch Set 1: (1 comment) File src/mainboard/gigabyte/ga-h61m-series/Kconfig.name: https://review.coreboot.org/c/coreboot/+/61541/comment/a68b7e67_2f3dd2d7 PS1, Line 12: select NO_UART_ON_SUPERIO out of topic the "select NO_UART_ON_SUPERIO" is odd in this file. maybe Kconfig file is the right place? -- To view, visit https://review.coreboot.org/c/coreboot/+/61541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d Gerrit-Change-Number: 61541 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 03:53:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Retype variables
by HAOUAS Elyes (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Angel Pons, Arthur Heymans, Kyösti Mälkki. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58697 ) Change subject: cpu/x86/smm: Retype variables ...................................................................... Patch Set 3: (1 comment) File src/include/cpu/x86/smm.h: https://review.coreboot.org/c/coreboot/+/58697/comment/7a84937f_47398cd5 PS3, Line 9: #include <types.h> stdint is duplicated as we have types.h -- To view, visit https://review.coreboot.org/c/coreboot/+/58697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Gerrit-Change-Number: 58697 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 03:41:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2022