coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
by Angel Pons (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 ) Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/61519/comment/fa7d3cce_58653ae4 PS4, Line 199: : if (eop_sent) { : printk(BIOS_ERR, "EOP already sent\n"); : return; : } : > IMO, we should check for HW mechanism, asked Intel for sharing some insights. […] I suggested adding this as there was a TODO comment, and I thought this would be better than nothing. However, if there's something better, let's use it instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 22:34:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: report developer mode to PSP
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61369 ) Change subject: psp_verstage: report developer mode to PSP ...................................................................... psp_verstage: report developer mode to PSP Add platform_report_mode function which report current developer mode status to the PSP. L1 widevine app in the PSP will use this information to select key box. BUG=b:211058864 TEST=build and boot guybrush TEST=build picasso chrome os boards Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/chipset.c 4 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 183f116..30f613a 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -33,6 +33,14 @@ return 0; } +void platform_report_mode(int developer_mode_enabled) +{ + if (developer_mode_enabled) + svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); + else + svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION); +} + /* Functions below are stub functions for not-yet-implemented PSP features. * These functions should be replaced with proper implementations later. diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 606b6a6..2e3b12f 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -65,5 +65,6 @@ uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table); int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, struct sha_generic_data *sha_op); +void platform_report_mode(int developer_mode_enabled); #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 05c14d6..9f34700 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -314,6 +314,8 @@ if (retval) reboot_into_recovery(ctx, retval); + platform_report_mode(vboot_developer_mode_enabled()); + post_code(POSTCODE_UPDATE_BOOT_REGION); /* diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c index 9577a5b..4bdb873 100644 --- a/src/soc/amd/picasso/psp_verstage/chipset.c +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -38,3 +38,9 @@ } return 0; } + +void platform_report_mode(int developer_mode_enabled) +{ + /* Picasso PSP doesn't support this */ + (void)developer_mode_enabled; +} 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Gerrit-Change-Number: 61369 Gerrit-PatchSet: 3 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... psp_verstage: add new svc for cezanne Add svc_set_platform_bootmode svc to cezanne. PSP will use this information to select proper widevine keybox. BUG=b:211058864 TEST=build guybrush Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/psp_verstage/svc.c M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 2 files changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index e04c702..78f7126 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -133,3 +133,10 @@ SVC_CALL3(SVC_CCP_DMA, spi_rom_offset, dest, size, retval); return retval; } + +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval); + return retval; +} diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 06e9def..ff2144d 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -50,6 +50,7 @@ #define SVC_READ_TIMER_VAL 0x68 #define SVC_SHA 0x69 #define SVC_CCP_DMA 0x6A +#define SVC_SET_PLATFORM_BOOT_MODE 0x6C struct mod_exp_params { char *pExponent; // Exponent address @@ -136,6 +137,19 @@ }; /* + * This is state that PSP manages internally. + * We only report BOOT_MODE_DEVELOPER or BOOT_MODE_PRODUCTION in verstage. + */ +enum chrome_platform_boot_mode +{ + NON_CHROME_BOOK_BOOT_MODE = 0x0, + CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, + CHROME_BOOK_BOOT_MODE_PRODUCTION = 0x2, + CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, + CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check +}; + +/* * Exit to the main Boot Loader. This does not return back to user application. * * Parameters: @@ -313,6 +327,14 @@ */ uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size); +/* + * Get the Platform boot mode from verstage. Production or developer + * + * Parameters: + * - boot mode + -----------------------------------------------------------------------------*/ +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode); + /* C entry point for the Bootloader Userspace Application */ void Main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: qualcomm/sc7280: Add support for edp and mdp driver
by build bot (Jenkins) (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Ravi kumar, Sudheer Amrabadi, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61342 ) Change subject: qualcomm/sc7280: Add support for edp and mdp driver ...................................................................... Patch Set 6: Verified+1 (2 comments) File src/mainboard/google/herobrine/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139721): https://review.coreboot.org/c/coreboot/+/61342/comment/6e4efd35_7276020a PS6, Line 61: if (display_init_required()) { suspect code indent for conditional statements (8, 24) File src/soc/qualcomm/sc7280/display/edp_ctrl.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139721): https://review.coreboot.org/c/coreboot/+/61342/comment/1b974ab5_2f4eb0c2 PS6, Line 863: ret = edp_start_link_train_2(ctrl,dpcd); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/61342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If89abb76028766b19450e756889a5d7776106f95 Gerrit-Change-Number: 61342 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Feb 2022 22:27:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Ethan Tsao (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Ethan Tsao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61389/comment/1d3e0366_5cbefad6 PS10, Line 12: TEST= apply platform soc folder to test > Check default offset for existing platform and update platform specific offset in KConfig under soc […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Feb 2022 22:23:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Ethan Tsao (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Subrata Banik, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61389 to look at the new patch set (#11). Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... soc/intel/graphics: Create Kconfig for shifting graphic memory base create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to shift graphic memory base if require. TEST= Check default offset for existing platform and update platform specific offset in KConfig under soc folder. BUG=b:216756721 Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com> --- M src/soc/intel/common/block/graphics/Kconfig M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/lib: Add CBMEM tag id to parse ddr information
by mturney mturney (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner, Arthur Heymans. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59194 ) Change subject: src/lib: Add CBMEM tag id to parse ddr information ...................................................................... Patch Set 21: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59194/comment/bb38b12f_d25fd26a PS19, Line 7: Added > Add Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f Gerrit-Change-Number: 59194 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 01 Feb 2022 22:21:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib: Add CBMEM tag id to parse ddr information
by mturney mturney (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner, Arthur Heymans. mturney mturney has uploaded a new patch set (#21) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59194 ) Change subject: src/lib: Add CBMEM tag id to parse ddr information ...................................................................... src/lib: Add CBMEM tag id to parse ddr information BUG=b:182963902,177917361 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59194/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/59194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f Gerrit-Change-Number: 59194 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: Add dram information to CBMEM table
by mturney mturney (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. mturney mturney has uploaded a new patch set (#21) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc/qualcomm/common: Add dram information to CBMEM table ...................................................................... soc/qualcomm/common: Add dram information to CBMEM table BUG=b:182963902,177917361 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 --- M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59195/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Parse DDR Information through coreboot tables
by mturney mturney (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. mturney mturney has uploaded a new patch set (#21) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: libpayload: Parse DDR Information through coreboot tables ...................................................................... libpayload: Parse DDR Information through coreboot tables BUG=b:182963902,177917361 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e --- M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c A src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 4 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59193/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2022