coreboot-gerrit February 2022

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Change in coreboot[master]: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61534 ) Change subject: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/61534/comment/393cf739_074c0018 PS2, Line 345: PSP_INIT_ESPI > Will this setup a soft fuse bit that PSP stage2 BL checks to initialize eSPI? Oops, I forgot to rename the usage in the Makefile.inc. -- To view, visit https://review.coreboot.org/c/coreboot/+/61534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Gerrit-Change-Number: 61534 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Feb 2022 21:37:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61534 to look at the new patch set (#3). Change subject: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI ...................................................................... soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It doesn't control if port 80s are written. This flag also doesn't currently control LPC init. The PSP is currently hard coded to remove any LPC init. BUG=b:215425753 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc 2 files changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/61534/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Gerrit-Change-Number: 61534 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device: Add support for PCIe Resizable BARs
by Tim Wawrzynczak (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 ) Change subject: device: Add support for PCIe Resizable BARs ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: Any thoughts on this one? File src/include/device/pci_def.h: https://review.coreboot.org/c/coreboot/+/61215/comment/e073758f_dfe3dfd9 PS2, Line 535: 0xe0 > for easy understanding […] Right now that macro isn't used in this file, so I didn't want to create inconsistencies. -- To view, visit https://review.coreboot.org/c/coreboot/+/61215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Gerrit-Change-Number: 61215 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 21:26:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/p8x7x-series: Refactor mainboard_get_spd()
by Keith Hui (Code Review) 01 Feb '22

01 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61540 ) Change subject: mb/asus/p8x7x-series: Refactor mainboard_get_spd() ...................................................................... mb/asus/p8x7x-series: Refactor mainboard_get_spd() This mainboard-specific hook of Sandy/Ivy native RAM init sequence, likely generated by autoport, is the same for all variants. Consolidate them into a separate unit at the baseboard level. The refactored routine is declared __weak, allowing future variants to override it should they deviate from the norm. Build tested on all variants. Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Makefile.inc A src/mainboard/asus/p8x7x-series/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c 8 files changed, 12 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/61540/1 diff --git a/src/mainboard/asus/p8x7x-series/Makefile.inc b/src/mainboard/asus/p8x7x-series/Makefile.inc index e339285..959207b 100644 --- a/src/mainboard/asus/p8x7x-series/Makefile.inc +++ b/src/mainboard/asus/p8x7x-series/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += variants/$(VARIANT_DIR)/early_init.c +romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_init.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/asus/p8x7x-series/early_init.c b/src/mainboard/asus/p8x7x-series/early_init.c new file mode 100644 index 0000000..ceee81f --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/early_init.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/sandybridge/raminit_native.h> + +void __weak mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c index 9f84b49..79b67f0 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -52,11 +51,3 @@ /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c index 3a297f9e..89f9eee 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -50,11 +49,3 @@ /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index dfcdd23..a616c7b 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/pei_data.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -42,14 +41,6 @@ */ } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index ddac440..a8f23df 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -9,7 +9,6 @@ #include <option.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/pei_data.h> @@ -46,14 +45,6 @@ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c index 42b4ebc..c16b055 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> @@ -47,11 +46,3 @@ /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c index 3a297f9e..89f9eee 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -50,11 +49,3 @@ /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/61540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Gerrit-Change-Number: 61540 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add Asus P8Z77-M
by Keith Hui (Code Review) 01 Feb '22

01 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61539 ) Change subject: Documentation: Add Asus P8Z77-M ...................................................................... Documentation: Add Asus P8Z77-M Change-Id: I01f990408c4552b69c04e849e7faaf9f51f24a51 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/p8z77-m.md 1 file changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/61539/1 diff --git a/Documentation/mainboard/asus/p8z77-m.md b/Documentation/mainboard/asus/p8z77-m.md new file mode 100644 index 0000000..0b00daf --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-m.md @@ -0,0 +1,138 @@ +# ASUS P8Z77-M + +This page describes how to run coreboot on the [ASUS P8Z77-M]. + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | yes | ++---------------------+----------------+ +``` + +The flash chip is located between the blue SATA ports. + +The main SPI flash cannot be written because Asus disables BIOSWE and +enables BLE/SMM_BWP flags in BIOS_CNTL for their latest bioses. +An external programmer is required. You must flash standalone, +flashing in-circuit doesn't work. The flash chip is socketed, so it's +easy to remove and reflash. Once coreboot is in place, flashrom +can be used for future updates. + +## Working + +- All USB2 ports (mouse/keyboard and pendrive) +- USB3 ports on rear (Booting with a Kingston DataTraveler G4 8GB loaded with SystemRescue 6.0.3) +- Gigabit Ethernet (RTL8111F) +- SATA3, SATA2 (tested on all ports, hot-swap not tested) + (Blue SATA2) (Blue SATA2) (White SATA3) + port 5 port 3 port 1 + port 6 port 4 port 2 + +- CPU Temp sensors and hardware monitor (some values don't make sense) + +- Native and MRC memory initialization + (please see [Native raminit compatibility] and [MRC memory compatibility]) + +- Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM + (VGA/DVI-D/HDMI tested and working) +- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3 + (Arch based)) +- Serial port +- PCI slot + Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested) + Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from + SeaBIOS) +- S3 suspend from Linux +- 2-channel analog audio (WAV playback by mplayer via back panel line out port) +- Windows 10 with libgfxinit high resolution framebuffer + +## Known issues + +- If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could + be reconfigured by the blob. + +- If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config. + Otherwise integrated graphics would fail with a black screen. + +- PCI POST card is not functional because the PCI bridge early init is not yet done. + +- The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for + an x8, and is electrically an x4 only. + +## Untested + +- Wake-on-LAN +- USB3 on header +- TPM header +- HDMI and S/PDIF audio out + +## Not working + +- PS/2 keyboard or mouse +- EHCI debugging (Debug port is on the 5-pin side of USB2_910 header) +- 4 and 6 channel analog audio out: Rear left and right audio is a muted + copy of front left and right audio, and the other two channels are silent. + +## Native (and MRC) raminit compatibility + +- OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600. + +- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but highly unstable + with obvious pattern of bit errors during memtest86+ runs. + +- Samsung PC3-10600U 2x2GB kit works at full rated speed. + +- Kingston KTH9600B-4G 2x8GB kit works at full rated speed. + +## Extra onboard buttons + +The board has two onboard buttons, and each has a related LED nearby. +What controls the LEDs and what the buttons control are unknown. + +- BIOS_FLBK + OEM firmware uses this button to facilitate a simple update mechanism + via a USB stick plugged into the bottom USB port of the USB/LAN stack. + +- MemOK! + OEM firmware uses this button for memory tuning related to overclocking. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8Z77-M]: https://www.asus.com/Motherboards/P8Z77M/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/c/coreboot/+/61539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f990408c4552b69c04e849e7faaf9f51f24a51 Gerrit-Change-Number: 61539 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add Asus P3B-F
by Keith Hui (Code Review) 01 Feb '22

01 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61538 ) Change subject: Documentation: Add Asus P3B-F ...................................................................... Documentation: Add Asus P3B-F Change-Id: I0cd6141bb8baa082d5558490533649f907f25dd1 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/p3b-f.md 1 file changed, 91 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/61538/1 diff --git a/Documentation/mainboard/asus/p3b-f.md b/Documentation/mainboard/asus/p3b-f.md new file mode 100644 index 0000000..bdf5d18 --- /dev/null +++ b/Documentation/mainboard/asus/p3b-f.md @@ -0,0 +1,91 @@ +# ASUS P3B-F + +This page describes how to run coreboot on the ASUS P3B-F mainboard. + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------------+ +| Type | Value | ++=====================+===========================+ +| Socketed flash | yes | ++---------------------+---------------------------+ +| Model | SST 39SF020A (or similar) | ++---------------------+---------------------------+ +| Size | 256 KiB | ++---------------------+---------------------------+ +| Package | DIP-32 | ++---------------------+---------------------------+ +| Write protection | no | ++---------------------+---------------------------+ +| Dual BIOS feature | no | ++---------------------+---------------------------+ +| Internal flashing | yse | ++---------------------+---------------------------+ +``` + +flashrom supports this mainboard since commit c7e9a6e15153684672bbadd1fc6baed8247ba0f6. +If you are using older versions of flashrom, below has to be done (with ACPI disabled!) +before flashrom can detect the flash chip: + +```bash + # rmmod w83781d + # modprobe i2c-dev + # i2cset 0 0x48 0x80 0x80 +``` + +## Working + +- Slot 1 and Socket 370 CPUs and their L1/L2 caches +- PS/2 keyboard with SeaBIOS (See [Known issues]) +- IDE hard drives +- USB +- PCI add-on cards +- AGP graphics cards +- Serial ports 1 and 2 +- Reboot + +## Known issues + +- PS/2 keyboard may not be usable until Linux has completely booted. With SeaBIOS + as payload, setting keyboard initialization timeout to 2500ms help. + +- The coreboot+SeaBIOS combination boots so quickly some IDE hard drives are not + yet ready by the time SeaBIOS attempts to boot from them. + +- i440BX does not support 256Mbit RAM modules. If installed, coreboot + will attempt to initialize them at half their capacity anyway + whereas vendor firmware will not boot at all. + +- ECC memory can be used, but ECC support is still pending. + +## Untested + +- Floppy +- Parallel port +- EDO memory +- ECC memory +- Infrared +- PC speaker + +## Not working + +- ACPI (Support is currently [under gerrit review](https://review.coreboot.org/c/coreboot/+/41098)) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/i440bx/index` | ++------------------+--------------------------------------------------+ +| Southbridge | i82371eb | ++------------------+--------------------------------------------------+ +| CPU | model_6xx | ++------------------+--------------------------------------------------+ +| Super I/O | winbond/w83977tf | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +[flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/c/coreboot/+/61538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd6141bb8baa082d5558490533649f907f25dd1 Gerrit-Change-Number: 61538 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add Asus P2B-LS
by Keith Hui (Code Review) 01 Feb '22

01 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61537 ) Change subject: Documentation: Add Asus P2B-LS ...................................................................... Documentation: Add Asus P2B-LS Change-Id: Ib885c4dd8472ed2b0a61c548f6ef652979a33153 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/p2b-ls.md 1 file changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/61537/1 diff --git a/Documentation/mainboard/asus/p2b-ls.md b/Documentation/mainboard/asus/p2b-ls.md new file mode 100644 index 0000000..7c6e423 --- /dev/null +++ b/Documentation/mainboard/asus/p2b-ls.md @@ -0,0 +1,108 @@ +# ASUS P2B-LS + +This page describes how to run coreboot on the ASUS P2B-LS mainboard. + +## Variants + +- P2B-LS +- P2B-L (Same circuit board with SCSI components unpopulated) +- P2B-S (Same circuit board with ethernet components unpopulated) + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------------+ +| Type | Value | ++=====================+===========================+ +| Socketed flash | yes | ++---------------------+---------------------------+ +| Model | SST 39SF020A (or similar) | ++---------------------+---------------------------+ +| Size | 256 KiB | ++---------------------+---------------------------+ +| Package | DIP-32 | ++---------------------+---------------------------+ +| Write protection | no | ++---------------------+---------------------------+ +| Dual BIOS feature | no | ++---------------------+---------------------------+ +| Internal flashing | yes | ++---------------------+---------------------------+ +``` + +[flashrom] works out of the box since 0.9.2. +Because of deficiency in vendor firmware, user needs to override the laptop +warning as prompted. Once coreboot is in place there will be no further issue. + +### CPU microcode considerations + +You need to "Allow use of binary-only repository" in menuconfig to download +the Intel CPU microcode binary blobs, otherwise the build may fail. + +This board by default includes microcode updates for 5 families of Intel CPUs +because of the wide variety of CPUs the board supports, directly or with an +adapter. These take up a third of the total flash space leaving only 20kB free +in the final cbfs image. If you start to run out of flash space, you +may have to omit some or all microcode updates by manually concatenating those +in 3rdparty/intel-microcode/intel-ucode that you actually have on hand. + +## Working + +- Slot 1 and Socket 370 CPUs and their L1/L2 caches +- PS/2 keyboard with SeaBIOS (See [Known issues]) +- IDE hard drives +- Ethernet (-LS, -L; Intel 82558) +- SCSI (-LS, -S; Adaptec AIC7890) +- USB +- ISA add-on cards +- PCI add-on cards +- AGP graphics card +- Floppy +- Serial ports 1 and 2 +- Reboot +- Soft off + +## Known issues + +- PS/2 keyboard may not be usable until Linux has completely booted. + With SeaBIOS as payload, setting keyboard initialization timeout to + 500ms should fix the issue. + +- i440BX does not support 256Mbit RAM modules. If installed, coreboot + will attempt to initialize them at half their capacity anyway + whereas vendor firmware will not boot at all. + +- ECC memory can be used, but ECC support is still pending. + +- At this time all SCSI ports have termination enabled. Support to + disable termination is pending. Note that the 68-pin SE port is + always terminated, even with vendor firmware. + +## Untested + +- Parallel port +- EDO memory +- Infrared +- PC speaker + +## Not working + +- S3 suspend to RAM + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/i440bx/index` | ++------------------+--------------------------------------------------+ +| Southbridge | i82371eb | ++------------------+--------------------------------------------------+ +| CPU | model_6xx | ++------------------+--------------------------------------------------+ +| Super I/O | winbond/w83977tf | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +[flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/c/coreboot/+/61537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib885c4dd8472ed2b0a61c548f6ef652979a33153 Gerrit-Change-Number: 61537 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
by Karthik Ramasubramanian (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61534 ) Change subject: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/61534/comment/ca5cb1b7_d9321b2b PS2, Line 345: PSP_INIT_ESPI Will this setup a soft fuse bit that PSP stage2 BL checks to initialize eSPI? -- To view, visit https://review.coreboot.org/c/coreboot/+/61534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Gerrit-Change-Number: 61534 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Feb 2022 21:12:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add support for Gemini Lake
by Sean Rhodes (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58537 to look at the new patch set (#4). Change subject: util/inteltool: Add support for Gemini Lake ...................................................................... util/inteltool: Add support for Gemini Lake Tested on: * StarLite Mk III (N5000) * StarLite Mk IV (N5030) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/geminilake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 323 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/58537/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48 Gerrit-Change-Number: 58537 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [Do not merge] soc/intel/alderlake: Enable USB2 port reset message on...
by Anil Kumar K (Code Review) 01 Feb '22

01 Feb '22

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61536 ) Change subject: [Do not merge] soc/intel/alderlake: Enable USB2 port reset message on Type-C ports ...................................................................... [Do not merge] soc/intel/alderlake: Enable USB2 port reset message on Type-C ports Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/usb.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/61536/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8284980..5695974 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -439,6 +439,9 @@ s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; + + if (config->usb2_ports[i].type_c) + params->PortResetMessageEnable[i] = 1; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index e339c72..70a367e 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -31,6 +31,7 @@ uint8_t tx_emp_enable; uint8_t pre_emp_bias; uint8_t pre_emp_bit; + uint8_t type_c; }; /* USB Overcurrent pins definition */ @@ -112,6 +113,7 @@ .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ } struct usb3_port_config { -- To view, visit https://review.coreboot.org/c/coreboot/+/61536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea Gerrit-Change-Number: 61536 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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