coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/brya: Lock FPMCU pins in brask and brya baseboards
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61502 ) Change subject: mb/google/brya: Lock FPMCU pins in brask and brya baseboards ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61502/comment/2a313c6e_4fcb1f15 PS3, Line 7: mb/google/brya: Allow mainboard to lock `FPMCU_*` GPIO PADs > suggestion: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5 Gerrit-Change-Number: 61502 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 20:33:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Lock FPMCU pins in brask and brya baseboards
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

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Change in coreboot[master]: mb/google/brya: Lock PCH WP pin in brask and brya baseboards
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61501 ) Change subject: mb/google/brya: Lock PCH WP pin in brask and brya baseboards ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61501/comment/a3a111f7_e90ce671 PS3, Line 7: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs > suggestion: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e Gerrit-Change-Number: 61501 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 20:33:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Lock PCH WP pin in brask and brya baseboards
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

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Change in coreboot[master]: mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

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Change in coreboot[master]: soc/intel/tigerlake: Use PMC IPC to disable HECI1
by Tim Wawrzynczak (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Maulik V Vaghela, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61457 ) Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1 ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Gerrit-Change-Number: 61457 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 20:32:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable PSP port 80s
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Raul Rangel has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/61535 ) Change subject: mb/google/guybrush: Enable PSP port 80s ...................................................................... mb/google/guybrush: Enable PSP port 80s Let's re-enable PSP post codes when running PSP verstage. The original reason we disabled POST codes was that it was causing problems during eSPI init in bootblock. Since we now init eSPI in PSP verstage, it's safe to re-enable them. We can now see post codes during S0i3 enter and exit. This will help when debugging resume or suspend hangs. Port 80 writes on suspend: ef000020 ef00ed00 ef00ed01 ef000021 <--new Port 80 writes on resume: 05 eea80025 eea90000 eea90100 eea90200 eea50000 eeae0000 eeae0004 eeaf0000 eeb00000 eec00000 eec00100 eec10000 eec40000 eec40500 eec40200 eefc0000 eefc0100 eec50000 ea00e0fc ea00abc1 ea00e60b ea00e60c ea00abe1 ea00abe2 ea00abe4 ea00abe5 ea00abeb ea00abec ea00abed ea00abee ea00abef ea00e10f ea00e098 ea00e099 ea00abf0 ea00abf2 ea00e10e ea00e60c ea00e101 ea00e090 ea00e091 ea00e098 ea00e099 ea00e098 ea00e099 ea00e100 ea00e60c ea00e0b0 ea00e0b4 ea00e0b7 ea00e60c ea00e0c2 ea00e0c4 ea00e0d3 ea00e60c ea00e10d ea00e0c1 ea00e10c ea00e60c ea00e0c4 e000 eec60000 eec20000 eec20800 b40000 eeb50000 eefc0000 eefc0300 ee070000 eed90000 eed90700 eeda0600 eedd0000 eecb0000 eecf0000 eecf0200 eee30000 eee30900 eee40000 ef000025 BUG=b:215425753 TEST=Boot/suspend/resume guybrush and verify post codes are printed Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie759f66be2b8ffac19145491a227752d4762a5b9 --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/61535/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie759f66be2b8ffac19145491a227752d4762a5b9 Gerrit-Change-Number: 61535 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Lock TPM pin in brask and brya baseboards
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61499 ) Change subject: mb/google/brya: Lock TPM pin in brask and brya baseboards ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61499/comment/405dac33_f2a1dbf8 PS3, Line 7: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs > Suggestion: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Gerrit-Change-Number: 61499 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 20:31:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Lock TPM pin in brask and brya baseboards
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Nick Vaccaro. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61499 to look at the new patch set (#4). Change subject: mb/google/brya: Lock TPM pin in brask and brya baseboards ...................................................................... mb/google/brya: Lock TPM pin in brask and brya baseboards This applies a configuration lock to the TPM I2C and IRQ GPIO for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d --- M src/mainboard/google/brya/variants/agah/gpio.c M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/anahera4es/gpio.c M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya4es/gpio.c M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/gimble/gpio.c M src/mainboard/google/brya/variants/gimble4es/gpio.c M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix4es/gpio.c M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/brya/variants/taeko4es/gpio.c M src/mainboard/google/brya/variants/taniks/gpio.c M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/volmar/gpio.c 21 files changed, 78 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/61499/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Gerrit-Change-Number: 61499 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61479 ) Change subject: cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION ...................................................................... cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION It was only evaluated on LEGACY_SMP_INIT path while model_106cx has used PARALLEL_MP for a long time. Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61479 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_106cx/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/lapic_cpu_init.c 3 files changed, 1 insertion(+), 57 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 76e0423..85f6288 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -8,6 +8,5 @@ select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS - select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 13ff65d..d021564 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -147,17 +147,6 @@ default y if NORTHBRIDGE_INTEL_IRONLAKE default n -config SERIALIZED_SMM_INITIALIZATION - bool - default n - help - On some CPUs, there is a race condition in SMM. - This can occur when both hyperthreads change SMM state - variables in parallel without coordination. - Setting this option serializes the SMM initialization - to avoid an ugly hang in the boot process at the cost - of a slightly longer boot time. - config X86_AMD_FIXED_MTRRS bool default n diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index c35888a..5f2b27b 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -332,37 +332,6 @@ } -static void smm_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) -{ - struct device *cpu; - int pre_count = atomic_read(&active_cpus); - - /* Loop through the cpus once to let them run through SMM relocator */ - - for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { - if (cpu->path.type != DEVICE_PATH_APIC) - continue; - - printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n", - cpu->path.apic.apic_id); - - if (cpu == bsp_cpu) - continue; - - if (!cpu->enabled) - continue; - - if (!start_cpu(cpu)) - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU 0x%02x would not start!\n", - cpu->path.apic.apic_id); - - /* FIXME: endless loop */ - while (atomic_read(&active_cpus) != pre_count) - ; - } -} - static void wait_other_cpus_stop(struct bus *cpu_bus) { struct device *cpu; @@ -422,8 +391,7 @@ if (is_smp_boot()) copy_secondary_start_to_lowest_1M(); - if (!CONFIG(SERIALIZED_SMM_INITIALIZATION)) - smm_init(); + smm_init(); /* Initialize the bootstrap processor */ cpu_initialize(0); @@ -435,18 +403,6 @@ if (is_smp_boot()) wait_other_cpus_stop(cpu_bus); - if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) { - /* At this point, all APs are sleeping: - * smm_init() will queue a pending SMI on all cpus - * and smm_other_cpus() will start them one by one */ - smm_init(); - - if (is_smp_boot()) { - last_cpu_index = 0; - smm_other_cpus(cpu_bus, info->cpu); - } - } - smm_init_completion(); if (is_smp_boot()) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d Gerrit-Change-Number: 61479 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2022