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Change subject: mb/google/brya: Allow mainboard to lock `FPMCU_*` GPIO PADs
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61502/comment/af234a61_aa34038d
PS3, Line 7: mb/google/brya: Allow mainboard to lock `FPMCU_*` GPIO PADs
suggestion:
```
mb/google/brya: Lock FPMCU pins in brask and brya baseboards
This applies a configuration lock to the FPMCU SPI and IRQ GPIOs
for all brya and brask variants.
```
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mturney mturney has uploaded a new patch set (#19) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59193 )
Change subject: libpayload: Parse DDR Information through coreboot tables
......................................................................
libpayload: Parse DDR Information through coreboot tables
BUG=b:182963902,177917361
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
---
M payloads/libpayload/include/libpayload.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
A src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
4 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59193/19
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Change subject: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61501/comment/319630d4_f094d925
PS3, Line 7: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
suggestion:
```
mb/google/brya: Lock PCH WP pin in brask and brya baseboards
This applies a configuration lock to the PCH write protect GPIO for
all brya and brask variants.
```
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Change subject: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61500/comment/875ef1eb_cca87a18
PS3, Line 7: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
suggestion:
```
mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards
This applies a configuration lock to the TPM IRQ pins for all
brya and brask variants.
```
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Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
......................................................................
Patch Set 3: Code-Review+2
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Hello build bot (Jenkins), Tim Wawrzynczak, Benson Leung, Prashant Malani,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
Change subject: mb/google/brya: Add custom PLD fields to device tree for brya0 and brya4es
......................................................................
mb/google/brya: Add custom PLD fields to device tree for brya0 and brya4es
For USB ports, we want to use custom PLD fields with more details to
indicate physical location. Custom PLD will also be added to other brya
variants in the future as we figure out physical port locations on those
devices. Type A port on MLB is removed since it is no longer used.
BUG=b:216490477
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung(a)google.com>
Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/brya4es/overridetree.cb
2 files changed, 112 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61388/11
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Hello build bot (Jenkins), Tim Wawrzynczak, Benson Leung, Prashant Malani,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61388
to look at the new patch set (#10).
Change subject: brya: Add custom PLD fields to device tree for brya0 and brya4es
......................................................................
brya: Add custom PLD fields to device tree for brya0 and brya4es
For USB ports, we want to use custom PLD fields with more details to
indicate physical location. Custom PLD will also be added to other brya
variants in the future as we figure out physical port locations on those
devices. Type A port on MLB is removed since it is no longer used.
BUG=b:216490477
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung(a)google.com>
Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/brya4es/overridetree.cb
2 files changed, 98 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61388/10
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 )
Change subject: Revert "util/crossgcc: Update gcc to 11.2"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Things you could try: […]
It’d be great, if you could try the suggestions above.
3. Did you test with another payload yet – like GRUB (and let coreboot run the Video BIOS option ROM).
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