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Change subject: soc/intel/common: Define enum cpu_perf_eff_type type for core types
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/61459/comment/79deca7a_68f53e83
PS3, Line 14: cpu_type
> correct, how about enum cpu_perf_eff_type?
Ack
https://review.coreboot.org/c/coreboot/+/61459/comment/6d96528a_a272c42a
PS3, Line 94: if (global_cpu_type[core_id])
> Ack
Ack
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Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph.
Hello Maulik V Vaghela, Paul Menzel, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61459
to look at the new patch set (#4).
Change subject: soc/intel/common: Define enum cpu_perf_eff_type type for core types
......................................................................
soc/intel/common: Define enum cpu_perf_eff_type type for core types
The patch defines enum values for small and big cores and uses them
to indicate the big or small core.
TEST=Verify the build for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e
---
M src/soc/intel/common/block/acpi/cpu_hybrid.c
1 file changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61459/4
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 )
Change subject: Revert "util/crossgcc: Update gcc to 11.2"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
if you have time, can you give a try to gcc-12?
https://review.coreboot.org/c/coreboot/+/61533
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58869 )
Change subject: drivers/intel/fsp2_0/include/fsp: fix fsp_header
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS9:
This still works on FSP 2.2 boards (i.e., google/brya0, Intel Alder Lake, multi-phase SI initialization still works), and also FSP 2.0 (i.e. google/dratini, Intel Comet Lake)
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