coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/common/cse: Make cse_disable_mei_devices a public function
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61430 ) Change subject: soc/intel/common/cse: Make cse_disable_mei_devices a public function ...................................................................... soc/intel/common/cse: Make cse_disable_mei_devices a public function This patch export cse_disable_mei_devices() function instead of marking it static. Other IA common code may need to get access to this function for making `heci1` device disable. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61430 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved EricR Lai: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 4e1c563..3fc4e2b 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -50,7 +50,7 @@ return true; } -static bool cse_disable_mei_devices(void) +bool cse_disable_mei_devices(void) { struct pmc_ipc_buffer req = { 0 }; struct pmc_ipc_buffer rsp; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index a558c32..9bf35da 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -486,4 +486,7 @@ */ bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf); +/* Function to make cse disable using PMC IPC */ +bool cse_disable_mei_devices(void); + #endif // SOC_INTEL_COMMON_CSE_H 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Gerrit-Change-Number: 61430 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Remove `mb_gpio_lock_config()` override function
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61503 ) Change subject: mb/google/brya: Remove `mb_gpio_lock_config()` override function ...................................................................... mb/google/brya: Remove `mb_gpio_lock_config()` override function This patch removes `lockable_brya_gpios` lists and `mb_gpio_lock_config` override function from brya baseboard directory as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to built and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61503 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index d037e40..9c99363 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -456,12 +456,3 @@ *num = 0; return NULL; } - -static struct gpio_lock_config lockable_brya_gpios[] = { -}; - -const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) -{ - *num = ARRAY_SIZE(lockable_brya_gpios); - return lockable_brya_gpios; -} 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Gerrit-Change-Number: 61503 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Lock FPMCU pins in brask and brya baseboards
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61502 ) Change subject: mb/google/brya: Lock FPMCU pins in brask and brya baseboards ...................................................................... mb/google/brya: Lock FPMCU pins in brask and brya baseboards This applies a configuration lock to the FPMCU SPI and IRQ GPIOs for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests `FPMCU_*` (F11-F13 and F15-F16) are locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61502 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 2 files changed, 5 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 203f6d9..5383aa7 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -230,17 +230,17 @@ /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), /* F14 : GSXDIN ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 7db7cd4..d037e40 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -458,11 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ - { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ - { GPP_F12, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D0_FPMCU_D1_R */ - { GPP_F15, GPIO_LOCK_CONFIG }, /* FPMCU_INT_L */ - { GPP_F16, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CS_FPMCU_R_L */ }; const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5 Gerrit-Change-Number: 61502 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Lock PCH WP pin in brask and brya baseboards
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61501 ) Change subject: mb/google/brya: Lock PCH WP pin in brask and brya baseboards ...................................................................... mb/google/brya: Lock PCH WP pin in brask and brya baseboards This applies a configuration lock to the PCH write protect GPIO for all brya and brask variants. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61501 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 2 files changed, 2 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 22b2c70..203f6d9 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -189,7 +189,7 @@ /* E14 : DDSP_HPDA ==> SOC_DP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> CLKREQ_8 */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> TP102 */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index fffbbc8..7db7cd4 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -188,7 +188,7 @@ /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ @@ -458,7 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ { GPP_F12, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D0_FPMCU_D1_R */ 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e Gerrit-Change-Number: 61501 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61500 ) Change subject: mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards ...................................................................... mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards This applies a configuration lock to the TPM IRQ pins for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests GSC_PCH_INT_ODL is locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61500 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 2 files changed, 2 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 40d73eb..22b2c70 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -29,7 +29,7 @@ /* A12 : SATAXPCIE1 ==> CLKREQ_9B */ PAD_NC(GPP_A12, NONE), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index ffc549e..fffbbc8 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -29,7 +29,7 @@ /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ @@ -458,7 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_A13, GPIO_LOCK_CONFIG }, /* GSC_PCH_INT_ODL */ { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62 Gerrit-Change-Number: 61500 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Lock TPM pin in brask and brya baseboards
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61499 ) Change subject: mb/google/brya: Lock TPM pin in brask and brya baseboards ...................................................................... mb/google/brya: Lock TPM pin in brask and brya baseboards This applies a configuration lock to the TPM I2C and IRQ GPIO for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61499 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/agah/gpio.c M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/anahera4es/gpio.c M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya4es/gpio.c M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/gimble/gpio.c M src/mainboard/google/brya/variants/gimble4es/gpio.c M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix4es/gpio.c M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/brya/variants/taeko4es/gpio.c M src/mainboard/google/brya/variants/taniks/gpio.c M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/volmar/gpio.c 21 files changed, 78 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index fbb9f0f..25c20f3 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -34,6 +34,10 @@ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), /* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 1d15a08..ab3ea66 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -70,6 +70,10 @@ /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), + /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H20 : IMGCLKOUT1 ==> NC */ PAD_NC(GPP_H20, NONE), /* H21 : IMGCLKOUT2 ==> Privacy screen */ diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c index 40dd56f..e7ded60 100644 --- a/src/mainboard/google/brya/variants/anahera4es/gpio.c +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -26,6 +26,10 @@ PAD_NC(GPP_B5, NONE), /* B6 : ISH_I2C0_SCL ==> NC */ PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 8757e40..8ea51d8 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -51,8 +51,6 @@ PAD_NC(GPP_B5, NONE), /* B6 : ISH_I2C0_SCL ==> NC */ PAD_NC(GPP_B6, NONE), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ /* B9 : NC */ /* B10 : NC */ /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ @@ -197,8 +195,10 @@ /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ - /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ - /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 268cddc..40d73eb 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -269,9 +269,9 @@ /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 88dbe0e..ffc549e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -458,8 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_B6, GPIO_LOCK_CONFIG }, /* PCH_I2C_TPM_SCL */ - { GPP_B7, GPIO_LOCK_CONFIG }, /* PCH_I2C_TPM_SDA */ { GPP_A13, GPIO_LOCK_CONFIG }, /* GSC_PCH_INT_ODL */ { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index f6171a6..4cf99df 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -7,6 +7,10 @@ static const struct pad_config board_id0_1_overrides[] = { /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), /* C3 : SML0CLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/brya4es/gpio.c b/src/mainboard/google/brya/variants/brya4es/gpio.c index f6171a6..4cf99df 100644 --- a/src/mainboard/google/brya/variants/brya4es/gpio.c +++ b/src/mainboard/google/brya/variants/brya4es/gpio.c @@ -7,6 +7,10 @@ static const struct pad_config board_id0_1_overrides[] = { /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), /* C3 : SML0CLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 3f09d5b..186c045 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -73,6 +73,10 @@ PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index c0749c3..fc43e94 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -79,6 +79,10 @@ /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA_P2 */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL_P2 */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c index 685b37a..5606733 100644 --- a/src/mainboard/google/brya/variants/gimble4es/gpio.c +++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c @@ -32,6 +32,10 @@ PAD_NC(GPP_B5, NONE), /* B6 : ISH_I2C0_SCL ==> NC */ PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 6f74e25..57975f7 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -63,6 +63,10 @@ /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index e30163c..36766f4 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -57,6 +57,10 @@ /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H19 : SRCCLKREQ4# ==> NC */ PAD_NC(GPP_H19, NONE), /* H21 : IMGCLKOUT2 ==> NC */ diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index f0d1c5d..42d2bcb 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -24,6 +24,10 @@ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index f9fd731..854b6ca 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -50,6 +50,10 @@ /* H3 : SX_EXIT_HOLDOFF# ==> NC */ PAD_NC(GPP_H3, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H20 : IMGCLKOUT1 ==> NC */ PAD_NC(GPP_H20, NONE), /* H21 : IMGCLKOUT2 ==> Privacy screen */ diff --git a/src/mainboard/google/brya/variants/redrix4es/gpio.c b/src/mainboard/google/brya/variants/redrix4es/gpio.c index afcb7e9..a04ebaf 100644 --- a/src/mainboard/google/brya/variants/redrix4es/gpio.c +++ b/src/mainboard/google/brya/variants/redrix4es/gpio.c @@ -20,6 +20,10 @@ /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index 4d93e54..a97aef8 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -97,6 +97,10 @@ /* F23 : BP105_CTRL ==> PP1050_CTRL */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c index 5d8badf..7105c09 100644 --- a/src/mainboard/google/brya/variants/taeko4es/gpio.c +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -34,6 +34,10 @@ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/taniks/gpio.c b/src/mainboard/google/brya/variants/taniks/gpio.c index 41f080b..05a68d1 100644 --- a/src/mainboard/google/brya/variants/taniks/gpio.c +++ b/src/mainboard/google/brya/variants/taniks/gpio.c @@ -115,6 +115,10 @@ /* F23 : BP105_CTRL ==> PP1050_CTRL */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index b7ade2e..6dbfb69 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -47,6 +47,10 @@ /* F19 : NC */ PAD_NC(GPP_F19, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H12 : I2C7_SDA ==> UWB_SDA */ PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), /* H13 : I2C7_SCL ==> UWB_SCL */ diff --git a/src/mainboard/google/brya/variants/volmar/gpio.c b/src/mainboard/google/brya/variants/volmar/gpio.c index 8c13b2f..3f3a181 100644 --- a/src/mainboard/google/brya/variants/volmar/gpio.c +++ b/src/mainboard/google/brya/variants/volmar/gpio.c @@ -72,6 +72,10 @@ /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Gerrit-Change-Number: 61499 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Subrata Banik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Ethan Tsao, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 11: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61389/comment/e87cf6a4_98a0dfc6 PS11, Line 7: soc/intel/graphics: Create Kconfig for shifting graphic memory base You might need to rework on commit msg else I agree with this problem statement. Also, may be something like SOC_INTEL_GFX_GMADR_BEHIND_GTT could be your parent Kconfig which decides if we need such additional arithmetic or not. SOC_INTEL_GFX_MEMBASE_OFFSET can be dependent on parent Kconfig File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/61389/comment/0c4e42e0_eec0be3b PS11, Line 122: printk(BIOS_INFO, "gfx memory bar(0x18) = 0x%lx GFX_MEMBASE_OFFSET = 0x%x\n", : memory_base, CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET); do we need this ? https://review.coreboot.org/c/coreboot/+/61389/comment/aeb97ec8_dadb3089 PS11, Line 129: memory_base = memory_base + CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET; memory_base += CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET; Assuming CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET is `0` unless overridden by SoC? Also, shouldn't this code sits at line above `if clause` ? Because the purpose of that if clause if to ensure memory_base is not zero. -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 11 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 06:53:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Kangheui Won (Code Review) 02 Feb '22

02 Feb '22

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h: https://review.coreboot.org/c/coreboot/+/61368/comment/38dc0e50_e02cf693 PS4, Line 145: NON_CHROME_BOOK_BOOT_MODE = 0x0, : CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, : CHROME_BOOK_BOOT_MODE_PRODUCTION = 0x2, : CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, : CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check > Please indent with a tab. It’d be great, if you sent a fix-up, as this seems to have slipped review. […] AMD releases PSP binary to Google with syscall headers. Most of (if not all) contents here are copied from there. And we try to minimize the difference between coreboot version and AMD version, that's the main reason we have few off-format things in here. I'm not sure what's the policy on src/vendorcode, but if we want proper formatting here it'd better to fix up whole file (e.g. line 35-53). WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 06:38:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Paul Menzel (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Kangheui Won. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h: https://review.coreboot.org/c/coreboot/+/61368/comment/497222e7_ba472c32 PS4, Line 145: NON_CHROME_BOOK_BOOT_MODE = 0x0, : CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, : CHROME_BOOK_BOOT_MODE_PRODUCTION = 0x2, : CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, : CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check Please indent with a tab. It’d be great, if you sent a fix-up, as this seems to have slipped review. Also, why is it necessary, to assign the values? Where are those defined? -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 06:24:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
by Sridhar Siricilla (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Anil Kumar K, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61536 ) Change subject: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea Gerrit-Change-Number: 61536 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 05:44:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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