coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Add stylus probe
by Henry Sun (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Evan Green, SH Kim, Tim Wawrzynczak, Marco Chen, Edward Doan, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61618 ) Change subject: mb/google/dedede/var/bugzzy: Add stylus probe ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Thanks for suggestion about SSFC. We would just add stylus probe only. […] Thanks for clarification. LGTM. I only have CR+1 grant, differ to Tim for CR+2 if the new update looks good to Tim too. -- To view, visit https://review.coreboot.org/c/coreboot/+/61618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42a63976b9521844f64180b550b16bac344f37 Gerrit-Change-Number: 61618 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Edward Doan <edoan(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:07:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Henry Sun <henrysun(a)google.com> Comment-In-Reply-To: Evan Green <evgreen(a)chromium.org> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Add stylus probe
by Henry Sun (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Evan Green, SH Kim, Tim Wawrzynczak, Marco Chen, Edward Doan, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61618 ) Change subject: mb/google/dedede/var/bugzzy: Add stylus probe ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42a63976b9521844f64180b550b16bac344f37 Gerrit-Change-Number: 61618 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Edward Doan <edoan(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:05:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config'
by HAOUAS Elyes (Code Review) 07 Feb '22

07 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61662 ) Change subject: sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config' ...................................................................... sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config' Change-Id: Iafe1a3476c0afa5ebfb75fb704429594e24e96f2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/ibexpeak/azalia.c 1 file changed, 11 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61662/1 diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 17db658..d4e639a 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -40,8 +40,6 @@ u8 *base; struct resource *res; u32 codec_mask; - u8 reg8; - u16 reg16; u32 reg32; /* Find base address */ @@ -61,33 +59,21 @@ reg32 |= RCBA32(0x2030) & 0xfe; pci_write_config32(dev, 0x120, reg32); - reg16 = pci_read_config16(dev, 0x78); - reg16 |= (1 << 11); - pci_write_config16(dev, 0x78, reg16); + pci_or_config16(dev, 0x78, 1 << 11); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - reg32 = pci_read_config32(dev, 0x114); - reg32 &= ~0xfe; - pci_write_config32(dev, 0x114, reg32); + pci_and_config32(dev, 0x114, ~0xfe); // Set VCi enable bit - reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); - pci_write_config32(dev, 0x120, reg32); + pci_or_config32(dev, 0x120, 1 << 31); // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + pci_or_config32(dev, 0xc4, 1 << 1); - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + pci_or_config8(dev, 0x43, 1 << 6); - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); - pci_write_config32(dev, 0xd0, reg32); + pci_and_config32(dev, 0xd0, ~(1 << 31)); /* Set Bus Master */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -103,14 +89,11 @@ /* Wait 1ms */ udelay(1000); - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode. This needs to be controlled via devicetree.cb + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status codec_mask = codec_detect(base); @@ -120,10 +103,7 @@ } /* Enable dynamic clock gating */ - reg8 = pci_read_config8(dev, 0x43); - reg8 &= ~0x7; - reg8 |= (1 << 2) | (1 << 0); - pci_write_config8(dev, 0x43, reg8); + pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0)); } static struct device_operations azalia_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/61662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe1a3476c0afa5ebfb75fb704429594e24e96f2 Gerrit-Change-Number: 61662 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/var/anahera4es: Add gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61661 ) Change subject: mb/google/var/anahera4es: Add gpios to lock ...................................................................... mb/google/var/anahera4es: Add gpios to lock Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. Also fix the gpio order of GPP_F19. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that anahera boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb --- M src/mainboard/google/brya/variants/anahera4es/gpio.c 1 file changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/61661/1 diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c index e7ded60..132dbf6 100644 --- a/src/mainboard/google/brya/variants/anahera4es/gpio.c +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -21,17 +21,17 @@ PAD_NC(GPP_A22, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), @@ -39,21 +39,21 @@ PAD_NC(GPP_C4, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ PAD_CFG_GPO(GPP_E0, 1, PLTRST), @@ -63,14 +63,13 @@ PAD_NC(GPP_E7, NONE), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), - /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), + /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/61661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb Gerrit-Change-Number: 61661 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/var/anahera: Add gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61660 ) Change subject: mb/google/var/anahera: Add gpios to lock ...................................................................... mb/google/var/anahera: Add gpios to lock Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. Also fix the gpio order of GPP_F19. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that anahera boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie50ba20a10ded184fd880be9ed288b90d346c22b --- M src/mainboard/google/brya/variants/anahera/gpio.c 1 file changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/61660/1 diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index ab3ea66..9483d56 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -21,13 +21,13 @@ PAD_NC(GPP_A22, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), @@ -35,21 +35,21 @@ PAD_NC(GPP_C4, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ PAD_CFG_GPO(GPP_E0, 1, PLTRST), @@ -59,14 +59,13 @@ PAD_NC(GPP_E7, NONE), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), - /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), + /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/61660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50ba20a10ded184fd880be9ed288b90d346c22b Gerrit-Change-Number: 61660 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/var/agah: Add gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, Tony Huang, Tim Wawrzynczak, Nick Vaccaro. EricR Lai has removed Wisley Chen from this change. ( https://review.coreboot.org/c/coreboot/+/61658 ) Change subject: mb/google/var/agah: Add gpios to lock ...................................................................... Removed reviewer Wisley Chen. -- To view, visit https://review.coreboot.org/c/coreboot/+/61658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839 Gerrit-Change-Number: 61658 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/var/agah: Add gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak. EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61658 ) Change subject: mb/google/var/agah: Add gpios to lock ...................................................................... mb/google/var/agah: Add gpios to lock Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that agah boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839 --- M src/mainboard/google/brya/variants/agah/gpio.c 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61658/1 diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 25c20f3..e8c5a18 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -29,17 +29,17 @@ PAD_CFG_GPI(GPP_A22, NONE, DEEP), /* B3 : PROC_GP2 ==> GPU_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C0 : SMBCLK ==> NC */ PAD_NC(GPP_C0, NONE), @@ -55,25 +55,25 @@ PAD_NC(GPP_C7, NONE), /* D0 : ISH_GP0 ==> NC */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> NC */ - PAD_NC(GPP_D1, NONE), + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), /* D2 : ISH_GP2 ==> LAN_PR_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> GPU_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> GPU_THERM_INT_ODL */ - PAD_CFG_GPI(GPP_D9, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D9, NONE, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */ - PAD_NC(GPP_D10, NONE), + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_OD */ PAD_CFG_GPO(GPP_E0, 0, DEEP), @@ -86,9 +86,9 @@ /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E9 : USB_OC0# ==> USB_A2_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */ - PAD_CFG_GPO(GPP_E10, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG), /* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */ @@ -105,15 +105,15 @@ /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), /* F11 : THC1_SPI2_CLK ==> NC */ - PAD_NC(GPP_F11, NONE), + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : GSXDOUT ==> NC */ - PAD_NC(GPP_F12, NONE), + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : GSXDOUT ==> NC */ - PAD_NC(GPP_F13, NONE), + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), /* F15 : GSXSRESET# ==> NC */ - PAD_NC(GPP_F15, NONE), + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), /* F16 : GSXCLK ==> NC */ - PAD_NC(GPP_F16, NONE), + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> NC */ PAD_NC(GPP_F19, NONE), /* F20 : EXT_PWR_GATE# ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839 Gerrit-Change-Number: 61658 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61656 to look at the new patch set (#4). Change subject: mb/google/brya: Add more gpios to lock ...................................................................... mb/google/brya: Add more gpios to lock Add rest of soc sensitive gpios to lock for brya. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/61656/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 Gerrit-Change-Number: 61656 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61657 to look at the new patch set (#3). Change subject: mb/google/brask: Add more gpios to lock ...................................................................... mb/google/brask: Add more gpios to lock Add rest of soc sensitive gpios to lock for brask. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brask boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c 1 file changed, 39 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61657/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 Gerrit-Change-Number: 61657 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/gpio: Add PAD_NC_LOCK support
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61655 to look at the new patch set (#5). Change subject: soc/intel/common/gpio: Add PAD_NC_LOCK support ...................................................................... soc/intel/common/gpio: Add PAD_NC_LOCK support Add PAD_NC_LOCK macro to support mainboard to lock NC pins as applicable. BUG=b:216583542 TEST=build passed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61655/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 Gerrit-Change-Number: 61655 Gerrit-PatchSet: 5 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2022