coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: qualcomm/sc7280: Add display external clock support in coreboot
by Sudheer Amrabadi (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Ravi kumar, Sudheer Amrabadi, mturney mturney. Sudheer Amrabadi has uploaded a new patch set (#15) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59611 ) Change subject: qualcomm/sc7280: Add display external clock support in coreboot ...................................................................... qualcomm/sc7280: Add display external clock support in coreboot Add support for EDP (Embedded DisplayPort) clocks in coreboot. This change supports the configuration and enablement of EDP PIXEL, LINK, LINK_INTF and AUX clocks. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 --- M src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/clock.h 2 files changed, 53 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59611/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/59611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Gerrit-Change-Number: 59611 Gerrit-PatchSet: 15 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/gimble: Group fw_config pad tables
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61151 ) Change subject: mb/google/brya/var/gimble: Group fw_config pad tables ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Patchset: PS1: LGTM with minor modification. File src/mainboard/google/brya/variants/gimble/fw_config.c: https://review.coreboot.org/c/coreboot/+/61151/comment/e5c394fe_371a7264 PS1, Line 70: 0 can we use enum instead `0` or `1` Isn't it more like `0` for disable and `1` for enable? -- To view, visit https://review.coreboot.org/c/coreboot/+/61151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9888950db254c6ccd9040ea7a61c049fd4a519c7 Gerrit-Change-Number: 61151 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 05:47:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/gpio: Add PAD_NC_LOCK support
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61655 ) Change subject: soc/intel/common/gpio: Add PAD_NC_LOCK support ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61655/comment/00ba4e3a_ace49c1a PS2, Line 9: lock needs for NC pins. > to lock NC PINs as applicable ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 Gerrit-Change-Number: 61655 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 05:38:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/gpio: Add PAD_NC_LOCK support
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61655 to look at the new patch set (#3). Change subject: soc/intel/common/gpio: Add PAD_NC_LOCK support ...................................................................... soc/intel/common/gpio: Add PAD_NC_LOCK support Add PAD_NC_LOCK macro to support mainboard to lock NC pins as applicable. BUG=b:216583542 TEST=build passed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61655/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 Gerrit-Change-Number: 61655 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add more gpios to lock
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61656 ) Change subject: mb/google/brya: Add more gpios to lock ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/61656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 Gerrit-Change-Number: 61656 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 05:37:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/gpio: Add PAD_NC_LOCK support
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61655 ) Change subject: soc/intel/common/gpio: Add PAD_NC_LOCK support ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61655/comment/b01abced_d0103f7f PS2, Line 9: lock needs for NC pins. to lock NC PINs as applicable ? -- To view, visit https://review.coreboot.org/c/coreboot/+/61655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 Gerrit-Change-Number: 61655 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 05:36:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61656 ) Change subject: mb/google/brya: Add more gpios to lock ...................................................................... mb/google/brya: Add more gpios to lock Add reset of soc sensitive gpios to lock for brya. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/61656/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 9c99363..b8d1761 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -80,7 +80,7 @@ /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), + PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */ PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ @@ -118,7 +118,7 @@ PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */ @@ -142,7 +142,7 @@ /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC(GPP_D12, NONE), + PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> CAM_PSW_L */ PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> SPKR_INT_L */ @@ -170,7 +170,7 @@ /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ PAD_CFG_GPO(GPP_E5, 1, DEEP), /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ - PAD_NC(GPP_E6, NONE), + PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), /* E7 : PROC_GP1 ==> EN_HPS_PWR */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ @@ -285,9 +285,9 @@ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H12, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), + PAD_NC_LOCK(GPP_H13, UP_20K, LOCK_CONFIG), /* H14 : NC */ PAD_NC(GPP_H14, NONE), /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 Gerrit-Change-Number: 61656 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
by Casper Chang (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60417 ) Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I tried latest coreboot on primus4es, the eMMC SKUs (PCIe3) could suspend properly but SSD SKUs (PCI […] Could we submit this CL to enable S0iX on ES CPU? -- To view, visit https://review.coreboot.org/c/coreboot/+/60417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac Gerrit-Change-Number: 60417 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 05:28:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
by Sridhar Siricilla (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 ) Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/include/soc/usb.h: https://review.coreboot.org/c/coreboot/+/61586/comment/d771973d_f6ff4a21 PS6, Line 98: #define USB2_PORT_MAX_TYPE_C(pin) { \ : .enable = 1, \ : .ocpin = (pin), \ : .tx_bias = USB2_BIAS_56P3MV, \ : .tx_emp_enable = USB2_PRE_EMP_ON, \ : .pre_emp_bias = USB2_BIAS_56P3MV, \ : .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ : .type_c = 1, \ : } : > I guess we could split this into two macros, […] Since there are consumers (across Brya family boards) of USB2_PORT_MAX, so I removed the macro intentionally. I think this is ok. -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 05:28:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: temp
by Bao Zheng (Code Review) 07 Feb '22

07 Feb '22

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61450 ) Change subject: temp ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/61450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5dbd1ca061fcc20e45dbc8fb1211a5a8144bbc Gerrit-Change-Number: 61450 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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coreboot-gerrit February 2022