Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61654 )
Change subject: temp.
......................................................................
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Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61618 )
Change subject: mb/google/dedede/var/bugzzy: Add probes for stylus and camera
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> dedede does have the SSFC (second source factory cache) enabled, which means there are effectively a […]
AFAIK, we don't have a proper way to probe mipi display for bugzzy, but not the mipi camera, and Tim's right, we defined the SSFC use for mipi in https://issuetracker.google.com/177055126
I'd suggest SH to check/discuss with Intel for whether the same way can be applied for bugzzy. Thank you!
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/gpio: Add PAD_NC_LOCK support
......................................................................
soc/intel/common/gpio: Add PAD_NC_LOCK support
Add PAD_NC_LOCK marco to support mainboard lock needs for NC pins.
BUG=b:216583542
TEST=build passed
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61655/2
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Change subject: soc/amd/cezanne: Add the fw SPL to fw.cfg
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61425/comment/29ef612f_fb7009c7
PS2, Line 7: SPL
> What is the SPL table? Is this a Cezanne specific binary, or is it chromeos specific?
Done
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Change subject: amdfwtool: Add SPL support
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61426/comment/b6cb908c_112cb7e4
PS3, Line 8:
> Please elaborate, what SPL is, and when and how it should be used.
Done
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Change subject: temp.
......................................................................
temp.
Change-Id: I200e9afbd92f805945c808558ffe304812c53a25
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
D util/coreboot-configurator/images/coreboot-configurator.gif
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/61654/1
diff --git a/util/coreboot-configurator/images/coreboot-configurator.gif b/util/coreboot-configurator/images/coreboot-configurator.gif
deleted file mode 100644
index 64e0a2f..0000000
--- a/util/coreboot-configurator/images/coreboot-configurator.gif
+++ /dev/null
Binary files differ
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Add the fw SPL to fw.cfg
......................................................................
soc/amd/cezanne: Add the fw SPL to fw.cfg
SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.
BUG=b:216096562
Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/fw.cfg
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/61425/3
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Change subject: amdfwtool: Add SPL support
......................................................................
amdfwtool: Add SPL support
SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.
BUG=b:216096562
Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61446 )
Change subject: soc/mediatek/mt8186: Fix issue of clearing watchdog status
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61446/comment/fa0718cb_cec6a37c
PS1, Line 9: .
> is wrong in CB:58835.
Done
https://review.coreboot.org/c/coreboot/+/61446/comment/d24176ea_af82e770
PS1, Line 9: Wrong implementation for
> The implementation of
Done
https://review.coreboot.org/c/coreboot/+/61446/comment/408cf0d4_1e41cd60
PS1, Line 10: The setting value should be:
: value of wdt mode | 0x22000000.
> The value written to the 'wdt_mode' register should be 'wdt_mode | 0x22000000' instead of 'wdt_statu […]
Done
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