coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Add stylus probe
by SH Kim (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Henry Sun, Evan Green, Tim Wawrzynczak, Marco Chen, Edward Doan, Karthik Ramasubramanian. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61618 ) Change subject: mb/google/dedede/var/bugzzy: Add stylus probe ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > AFAIK, we don't have a proper way to probe mipi display for bugzzy, but not the mipi camera, and Tim […] Thanks for suggestion about SSFC. We would just add stylus probe only. As we discussed internally, we don't need to probe camera device for now. We though probing MIPI camera takes about 2 seconds before (discussed in b:214587421), but the 2 seconds was from ME factory mode. Probing MIPI camera just takes about 100 ms, it seems not critical delay. We can use SSFC for probing mipi camera if we decide to add another camera IC later. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/61618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42a63976b9521844f64180b550b16bac344f37 Gerrit-Change-Number: 61618 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Edward Doan <edoan(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 06:28:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Henry Sun <henrysun(a)google.com> Comment-In-Reply-To: Evan Green <evgreen(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/nivviks: Initialise overridetree
by Kangheui Won (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Usha P. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61605 ) Change subject: mb/google/brya/var/nivviks: Initialise overridetree ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 Gerrit-Change-Number: 61605 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 06:16:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61657 ) Change subject: mb/google/brask: Add more gpios to lock ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61657/comment/1ddccca1_3802c53c PS1, Line 9: reset > rest ? thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/61657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 Gerrit-Change-Number: 61657 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 06:15:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Hello Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61657 to look at the new patch set (#2). Change subject: mb/google/brask: Add more gpios to lock ...................................................................... mb/google/brask: Add more gpios to lock Add rest of soc sensitive gpios to lock for brask. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brask boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c 1 file changed, 39 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61657/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 Gerrit-Change-Number: 61657 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61656 to look at the new patch set (#3). Change subject: mb/google/brya: Add more gpios to lock ...................................................................... mb/google/brya: Add more gpios to lock Add rest of soc sensitive gpios to lock for brya. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/61656/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 Gerrit-Change-Number: 61656 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask: Add more gpios to lock
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61657 ) Change subject: mb/google/brask: Add more gpios to lock ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61657/comment/b824ca58_25386546 PS1, Line 9: reset rest ? -- To view, visit https://review.coreboot.org/c/coreboot/+/61657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 Gerrit-Change-Number: 61657 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 06:13:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak. EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61657 ) Change subject: mb/google/brask: Add more gpios to lock ...................................................................... mb/google/brask: Add more gpios to lock Add reset of soc sensitive gpios to lock for brask. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brask boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c 1 file changed, 39 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61657/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 5383aa7..888048a 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -35,7 +35,7 @@ /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG), /* A17 : DISP_MISCC ==> NC */ PAD_NC(GPP_A17, NONE), /* A18 : DDSP_HPDB ==> HDMI_HPD */ @@ -58,17 +58,17 @@ /* B2 : VRALERT# ==> M2_SSD_PLA_L */ PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> NC */ - PAD_NC(GPP_B7, NONE), + PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> NC */ - PAD_NC(GPP_B8, NONE), + PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG), /* B9 : NC */ PAD_NC(GPP_B9, NONE), /* B10 : NC */ @@ -80,13 +80,13 @@ /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> PWM_PP3300_BUZZER */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_B14, NONE, NF1, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> TP159 */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> NC */ - PAD_NC(GPP_B16, NONE), + PAD_NC_LOCK(GPP_B16, NONE, LOCK_CONFIG), /* B17 : I2C5_SCL ==> NC */ - PAD_NC(GPP_B17, NONE), + PAD_NC_LOCK(GPP_B17, NONE, LOCK_CONFIG), /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ PAD_NC(GPP_B18, NONE), /* B19 : NC */ @@ -118,13 +118,13 @@ PAD_NC(GPP_C7, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), /* D3 : ISH_GP3 ==> EN_NFC_PWR */ - PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG), /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_D4, 1, DEEP), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ @@ -136,34 +136,34 @@ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG), /* D11 : ISH_SPI_MISO ==> DDIA_DP_CTRLCLK */ - PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_D11, NONE, NF2, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> DDIA_DP_CTRLDATA */ - PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_D12, NONE, NF2, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> TP97 */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> TP93 */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ - PAD_CFG_GPI(GPP_D17, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* E0 : SATAXPCIE0 ==> CLKREQ_9 */ PAD_NC(GPP_E0, NONE), /* E1 : THC0_SPI1_IO2 ==> NC */ - PAD_NC(GPP_E1, NONE), + PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG), /* E2 : THC0_SPI1_IO3 ==> NC */ - PAD_NC(GPP_E2, NONE), + PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG), /* E3 : PROC_GP0 ==> TP94644 */ PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ @@ -171,21 +171,21 @@ /* E5 : SATA_DEVSLP1 ==> NC */ PAD_NC(GPP_E5, NONE), /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ - PAD_NC(GPP_E6, NONE), + PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), /* E7 : PROC_GP1 ==> TP94643 */ PAD_NC(GPP_E7, NONE), /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ PAD_CFG_GPO(GPP_E8, 1, DEEP), /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E11 : THC0_SPI1_CLK ==> NC */ - PAD_NC(GPP_E11, NONE), + PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> NC */ - PAD_NC(GPP_E12, NONE), + PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG), /* E13 : THC0_SPI1_IO2 ==> NC */ - PAD_NC(GPP_E13, NONE), + PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> SOC_DP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ @@ -236,15 +236,15 @@ /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), /* F14 : GSXDIN ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_F14, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_F14, 1, LOCK_CONFIG), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* F20 : EXT_PWR_GATE# ==> TP94669 */ @@ -263,7 +263,7 @@ /* H2 : GPPH2_BOOT_STRAP3 */ PAD_NC(GPP_H2, NONE), /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H3, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG), /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ @@ -281,9 +281,9 @@ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H12, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), /* H14 : NC */ PAD_NC(GPP_H14, NONE), /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159 Gerrit-Change-Number: 61657 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add more gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61656 to look at the new patch set (#2). Change subject: mb/google/brya: Add more gpios to lock ...................................................................... mb/google/brya: Add more gpios to lock Add reset of soc sensitive gpios to lock for brya. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/61656/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 Gerrit-Change-Number: 61656 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/gpio: Add PAD_NC_LOCK support
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61655 to look at the new patch set (#4). Change subject: soc/intel/common/gpio: Add PAD_NC_LOCK support ...................................................................... soc/intel/common/gpio: Add PAD_NC_LOCK support Add PAD_NC_LOCK macro to support mainboard to lock NC pins as applicable. BUG=b:216583542 TEST=build passed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61655/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518 Gerrit-Change-Number: 61655 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7280: Add display external clock support in coreboot
by Sudheer Amrabadi (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Shelley Chen, Ravi kumar. Sudheer Amrabadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59611 ) Change subject: qualcomm/sc7280: Add display external clock support in coreboot ...................................................................... Patch Set 15: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59611/comment/85a62260_ca8a472e PS11, Line 13: BUG=b:182963902,216687885 > BUG=b:182963902, b:216687885 Ack https://review.coreboot.org/c/coreboot/+/59611/comment/ddbdafd7_5d1bbe70 PS11, Line 14: development > development Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Gerrit-Change-Number: 59611 Gerrit-PatchSet: 15 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 05:57:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2022