coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/var/banshee: Add gpios to lock
by Ivy Jian (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61663 ) Change subject: mb/google/var/banshee: Add gpios to lock ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/banshee/gpio.c: https://review.coreboot.org/c/coreboot/+/61663/comment/30cfc597_1efa496b PS1, Line 148: PAD_NC(GPP_E17, NONE), Should this be PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG)? -- To view, visit https://review.coreboot.org/c/coreboot/+/61663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee Gerrit-Change-Number: 61663 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:43:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/var/felwinter: Add gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61666 ) Change subject: mb/google/var/felwinter: Add gpios to lock ...................................................................... mb/google/var/felwinter: Add gpios to lock Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that felwinter boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic1e0bfc53b74bd5af9ac8d598bb80833499dd997 --- M src/mainboard/google/brya/variants/felwinter/gpio.c 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/61666/1 diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 186c045..2dff34e 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -12,31 +12,31 @@ /* A8 : SRCCLKREQ7# ==> PEN_DET_ODL */ PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B6 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> EN_PP5000_PEN */ PAD_CFG_GPO(GPP_C4, 1, DEEP), /* D0 : ISH_GP0 ==> NC */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> NC */ - PAD_NC(GPP_D1, NONE), + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), /* D2 : ISH_GP2 ==> NC */ - PAD_NC(GPP_D2, NONE), + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), /* E3 : PROC_GP0 ==> NC */ @@ -44,9 +44,9 @@ /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E9 : USB_OC0# ==> NC */ - PAD_NC(GPP_E9, NONE), + PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ @@ -60,15 +60,15 @@ /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), /* F11 : THC1_SPI2_CLK ==> NC */ - PAD_NC(GPP_F11, NONE), + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : GSXDOUT ==> NC */ - PAD_NC(GPP_F12, NONE), + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : GSXDOUT ==> NC */ - PAD_NC(GPP_F13, NONE), + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), /* F15 : GSXSRESET# ==> NC */ - PAD_NC(GPP_F15, NONE), + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), /* F16 : GSXCLK ==> NC */ - PAD_NC(GPP_F16, NONE), + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e0bfc53b74bd5af9ac8d598bb80833499dd997 Gerrit-Change-Number: 61666 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/taeko: Add WiFi SAR table for taeko
by Kevin Chang (Code Review) 07 Feb '22

07 Feb '22

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61665 ) Change subject: mb/google/brya/var/taeko: Add WiFi SAR table for taeko ...................................................................... mb/google/brya/var/taeko: Add WiFi SAR table for taeko Add WiFi SAR table for taeko. BUG=b:206901900 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I061dc798ae7177d05bc50648cfda46a3eec2c912 --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/taeko/Makefile.inc A src/mainboard/google/brya/variants/taeko/variant.c M src/mainboard/google/brya/variants/taeko4es/Makefile.inc A src/mainboard/google/brya/variants/taeko4es/variant.c 5 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/61665/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 0a3b1d9..ccbeb05 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -128,12 +128,18 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENESYSLOGIC_GL9763E + select USE_SAR + select WIFI_SAR_CBFS + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_TAEKO4ES bool "-> Taeko4ES" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENESYSLOGIC_GL9763E + select USE_SAR + select WIFI_SAR_CBFS + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_TANIKS bool "-> Taniks" diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.inc b/src/mainboard/google/brya/variants/taeko/Makefile.inc index c61f75a..396e5be 100644 --- a/src/mainboard/google/brya/variants/taeko/Makefile.inc +++ b/src/mainboard/google/brya/variants/taeko/Makefile.inc @@ -7,3 +7,5 @@ ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/taeko/variant.c b/src/mainboard/google/brya/variants/taeko/variant.c new file mode 100644 index 0000000..6a79780 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} diff --git a/src/mainboard/google/brya/variants/taeko4es/Makefile.inc b/src/mainboard/google/brya/variants/taeko4es/Makefile.inc index c61f75a..396e5be 100644 --- a/src/mainboard/google/brya/variants/taeko4es/Makefile.inc +++ b/src/mainboard/google/brya/variants/taeko4es/Makefile.inc @@ -7,3 +7,5 @@ ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/taeko4es/variant.c b/src/mainboard/google/brya/variants/taeko4es/variant.c new file mode 100644 index 0000000..6a79780 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061dc798ae7177d05bc50648cfda46a3eec2c912 Gerrit-Change-Number: 61665 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/ibexpeak/early_thermal.c: Reduce difference with bd82x6x
by HAOUAS Elyes (Code Review) 07 Feb '22

07 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61664 ) Change subject: sb/intel/ibexpeak/early_thermal.c: Reduce difference with bd82x6x ...................................................................... sb/intel/ibexpeak/early_thermal.c: Reduce difference with bd82x6x Change-Id: I470957b395f1010668f1c9d2c2c6ae7cb88e89a7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/ibexpeak/early_thermal.c 1 file changed, 19 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/61664/1 diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index d8b9195..0accfc6 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -6,35 +6,33 @@ #include "cpu/intel/model_2065x/model_2065x.h" #include <cpu/x86/msr.h> +/* Temporary address for the thermal BAR */ +#define TBARB_TEMP 0x40000000 + /* Early thermal init, must be done prior to giving ME its memory - which is done at the end of raminit. */ + which is done at the end of raminit */ void early_thermal_init(void) { - pci_devfn_t dev; - msr_t msr; - + const pci_devfn_t dev; dev = PCI_DEV(0x0, 0x1f, 0x6); - /* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); + /* Program address for temporary BAR */ + pci_write_config32(dev, 0x40, TBARB_TEMP); pci_write_config32(dev, 0x44, 0x0); - /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) | 5); + /* Activate temporary BAR */ + pci_or_config32(dev, 0x40, 5); - /* Perform init. */ - /* Configure TJmax. */ - msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6); - /* Northbridge temperature slope and offset. */ - write16((u16 *)0x40000016, 0x7746); - /* Enable thermal data reporting, processor, PCH and northbridge. */ - write16((u16 *)0x4000001a, - (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0); + /* Perform init */ + /* Configure TJmax */ + const msr_t msr = rdmsr(MSR_TEMPERATURE_TARGET); + write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6); + /* Northbridge temperature slope and offset */ + write16p(TBARB_TEMP + 0x16, 0x7746); + /* Enable thermal data reporting, processor, PCH and northbridge */ + write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0); - /* Disable temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) & ~1); + /* Disable temporary BAR */ + pci_and_config32(dev, 0x40, ~1); pci_write_config32(dev, 0x40, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I470957b395f1010668f1c9d2c2c6ae7cb88e89a7 Gerrit-Change-Number: 61664 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/var/banshee: Add gpios to lock
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Ivy Jian, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61663 ) Change subject: mb/google/var/banshee: Add gpios to lock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee Gerrit-Change-Number: 61663 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:22:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/var/anahera4es: Add gpios to lock
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Chen Wisley, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61661 ) Change subject: mb/google/var/anahera4es: Add gpios to lock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb Gerrit-Change-Number: 61661 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:22:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/var/anahera: Add gpios to lock
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Chen Wisley, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61660 ) Change subject: mb/google/var/anahera: Add gpios to lock ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/anahera/gpio.c: https://review.coreboot.org/c/coreboot/+/61660/comment/8e453d9f_93a954d9 PS1, Line 67: /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ : PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), you can submit a different CL if you wish -- To view, visit https://review.coreboot.org/c/coreboot/+/61660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50ba20a10ded184fd880be9ed288b90d346c22b Gerrit-Change-Number: 61660 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:22:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/var/agah: Add gpios to lock
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tony Huang, Chen Wisley, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61658 ) Change subject: mb/google/var/agah: Add gpios to lock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839 Gerrit-Change-Number: 61658 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:21:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/r8168: Add ASPM control mechanism
by Rory Liu (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Zhuohao Lee. Rory Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61267 ) Change subject: drivers/net/r8168: Add ASPM control mechanism ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/61267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I944dbf04d3ca19df4de224540bee538bff4d1f12 Gerrit-Change-Number: 61267 Gerrit-PatchSet: 3 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 07:17:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/var/banshee: Add gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61663 ) Change subject: mb/google/var/banshee: Add gpios to lock ...................................................................... mb/google/var/banshee: Add gpios to lock Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage' Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee --- M src/mainboard/google/brya/variants/banshee/gpio.c 1 file changed, 28 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/61663/1 diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 8ea51d8..847569f 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -45,12 +45,12 @@ /* B1 : SOC_VID1 */ /* B2 : VRALERT# ==> M2_SSD_PLA_L */ /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B4 : PROC_GP3 ==> SSD_PERST_L */ /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B9 : NC */ /* B10 : NC */ /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ @@ -58,7 +58,7 @@ /* B13 : PLTRST# ==> PLT_RST_L */ /* B14 : SPKR ==> GPP_B14_STRAP */ /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ @@ -82,13 +82,13 @@ /* C7 : SML1DATA ==> USI_INT */ /* D0 : ISH_GP0 ==> NC */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> NC */ - PAD_NC(GPP_D1, NONE), + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), /* D2 : ISH_GP2 ==> NC */ - PAD_NC(GPP_D2, NONE), + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), @@ -100,28 +100,28 @@ /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */ - PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> USI_RST_L */ - PAD_CFG_GPO(GPP_D18, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D18, 0, LOCK_CONFIG), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), /* E1 : THC0_SPI1_IO2 ==> NC */ - PAD_NC(GPP_E1, NONE), + PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG), /* E2 : THC0_SPI1_IO3 ==> NC */ - PAD_NC(GPP_E2, NONE), + PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG), /* E3 : PROC_GP0 ==> NC */ PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ @@ -133,13 +133,13 @@ /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E11 : THC0_SPI1_CLK ==> NC */ - PAD_NC(GPP_E11, NONE), + PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> NC */ - PAD_NC(GPP_E12, NONE), + PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG), /* E13 : THC0_SPI1_IO2 ==> NC */ - PAD_NC(GPP_E13, NONE), + PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ /* E15 : RSVD_TP ==> PCH_WP_OD */ /* E16 : RSVD_TP ==> NC */ @@ -168,16 +168,16 @@ /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ /* F10 : GPPF10_STRAP */ /* F11 : THC1_SPI2_CLK ==> NC */ - PAD_NC(GPP_F11, NONE), + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : GSXDOUT ==> NC */ - PAD_NC(GPP_F12, NONE), + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : GSXDOUT ==> NC */ - PAD_NC(GPP_F13, NONE), + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ /* F15 : GSXSRESET# ==> NC */ - PAD_NC(GPP_F15, NONE), + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), /* F16 : GSXCLK ==> NC */ - PAD_NC(GPP_F16, NONE), + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ /* F19 : SRCCLKREQ6# ==> NC */ @@ -205,9 +205,9 @@ PAD_NC(GPP_H9, NONE), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ /* H12 : I2C7_SDA ==> NC */ - PAD_NC(GPP_H12, NONE), + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), /* H14 : NC */ /* H15 : DDPB_CTRLCLK ==> NC */ PAD_NC(GPP_H15, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/61663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee Gerrit-Change-Number: 61663 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2022