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Change subject: src/lib: Add CBMEM tag id to parse ddr information
......................................................................
src/lib: Add CBMEM tag id to parse ddr information
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59194/24
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Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
Patch Set 13: Code-Review+2
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Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/5b373175_5dc30a5e
PS8, Line 1022: if (cse_is_hfs1_spi_protected())
> > nit: I'd write the check as […]
Yeah, I agree it's a miss from end.
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Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
Patch Set 13: Code-Review+2
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Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Nick Vaccaro, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61520
to look at the new patch set (#12).
Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
soc/intel/common/cse: Add function to perform global reset lock
This patch implements `cse_control_global_reset_lock()` as per ME BWG
(doc: 627331) recommendation.
It is recommended that BIOS should set this bit early on in the boot
sequence, and then clear it and set the CF9LOCK bit prior to loading
the OS in both an Intel CSME Enabled and a Intel CSME Disabled system.
Note: For CSE-Lite SKUs BIOS should set CF9LOCK bit unconditionally.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61520/12
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Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/5527801a_66a17217
PS8, Line 1022: if (cse_is_hfs1_spi_protected())
> nit: I'd write the check as
> `if (CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU) || cse_cse_is_hfs1_spi_protected())` so that the function call can get optimised out for CSE Lite.
Yes, that makes sense to me as well because reading the recommendation from Sridhar looks like for CSE lite SKU, those original ME BWG recommendation is not relevant.
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Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/8441f918_acfe2ecc
PS8, Line 1022: if (cse_is_hfs1_spi_protected())
> > >Any pointer to about who shares this recommendation and in what form ? I mean any document as suc […]
nit: I'd write the check as
`if (CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU) || cse_cse_is_hfs1_spi_protected())` so that the function call can get optimised out for CSE Lite.
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Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61665 )
Change subject: mb/google/brya/var/taeko: Add WiFi SAR table for taeko
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Set Ready For Review
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