coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/fizz: update VBT for karma variant
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61579 ) Change subject: mb/google/fizz: update VBT for karma variant ...................................................................... mb/google/fizz: update VBT for karma variant Extracted from firmware image: bios-karma.ro-11343-22-0.rw-11343-22-0.bin Change-Id: Ic4165523a9114f748174c272ee206dfea80f4541 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61579 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/fizz/variants/karma/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/fizz/variants/karma/data.vbt b/src/mainboard/google/fizz/variants/karma/data.vbt index dbbf475..460c5ee 100644 --- a/src/mainboard/google/fizz/variants/karma/data.vbt +++ b/src/mainboard/google/fizz/variants/karma/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/61579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4165523a9114f748174c272ee206dfea80f4541 Gerrit-Change-Number: 61579 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61581 ) Change subject: mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support ...................................................................... mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support Add ID "AMDI5619" for machine driver to support ALC5682I-VS + ACL1019 combination. BUG=b:211835769 TEST=Build dewatt, codec is functional with new machine driver. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ic6cb3bda7b8f1b96485f7b868200c94e6c720c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61581 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Yu-hsuan Hsu <yuhsuan(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved Yu-hsuan Hsu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index eb3d00d..6cb8293 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -4,6 +4,14 @@ device domain 0 on device ref gpp_bridge_1 off end # no SD device ref gpp_bridge_2 off end # no WWAN + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref acp on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5619"" + device generic 0.0 on end + end + end # Audio + end end # domain register "slow_ppt_limit_mW" = "25000" -- To view, visit https://review.coreboot.org/c/coreboot/+/61581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6cb3bda7b8f1b96485f7b868200c94e6c720c7b Gerrit-Change-Number: 61581 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/amd/cezanne: Add support to map UARTs
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61606 ) Change subject: vc/amd/cezanne: Add support to map UARTs ...................................................................... vc/amd/cezanne: Add support to map UARTs This will allow coreboot to directly write to the UART controller. BUG=b:215599230 TEST=Try mapping the uart on guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61606 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 4cf9e70..d88bfe1 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -88,10 +88,17 @@ FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, + FCH_IO_DEVICE_UART, FCH_IO_DEVICE_END, }; +enum fch_uart_id { + FCH_UART_ID_0 = 0, + FCH_UART_ID_1 = 1, + FCH_UART_ID_MAX, +}; + enum fch_i2c_controller_id { FCH_I2C_CONTROLLER_ID_0 = 0, FCH_I2C_CONTROLLER_ID_1 = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/61606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 Gerrit-Change-Number: 61606 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Define enum cpu_perf_eff_type type for core types
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61459 ) Change subject: soc/intel/common: Define enum cpu_perf_eff_type type for core types ...................................................................... soc/intel/common: Define enum cpu_perf_eff_type type for core types The patch defines enum values for small and big cores and uses them to indicate the big or small core. TEST=Verify the build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61459 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 70e6329..4335a46 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -11,6 +11,11 @@ #define CPPC_NOM_FREQ_IDX 22 #define CPPC_NOM_PERF_IDX 3 +enum cpu_perf_eff_type { + CPU_TYPE_SMALL, + CPU_TYPE_BIG, +}; + DECLARE_SPIN_LOCK(cpu_lock); static u8 global_cpu_type[CONFIG_MAX_CPUS]; @@ -46,7 +51,7 @@ u8 cpu_index = get_cpu_index(); if (is_big_core()) - global_cpu_type[cpu_index] = 1; + global_cpu_type[cpu_index] = CPU_TYPE_BIG; spin_unlock(&cpu_lock); } @@ -86,7 +91,7 @@ acpi_get_cpu_nomi_perf(&small_core_nom_perf, &big_core_nom_perf); - if (global_cpu_type[core_id]) + if (global_cpu_type[core_id] == CPU_TYPE_BIG) acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, big_core_nom_perf); else acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, -- To view, visit https://review.coreboot.org/c/coreboot/+/61459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e Gerrit-Change-Number: 61459 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/apollolake: Convert to ASL 2.0
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61243 ) Change subject: soc/intel/apollolake: Convert to ASL 2.0 ...................................................................... soc/intel/apollolake: Convert to ASL 2.0 Change-Id: Ieb362b5be05421b6ad2b2a3126c2943b7d55d135 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61243 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/apollolake/acpi/gpio.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/acpi/scs.asl 7 files changed, 80 insertions(+), 84 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 1fe58e1..f5795ef 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -25,8 +25,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM0_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -55,8 +55,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM1_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -85,8 +85,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM2_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -115,8 +115,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM3_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -137,9 +137,9 @@ * local1 - to toggle Tx pin of Dw0 * local2 - Address of PERST */ - Store (Arg0, Local2) - Store (\_SB.GPC0 (Local2), Local1) - Or (Local1, PAD_CFG0_TX_STATE, Local1) + Local2 = Arg0 + Local1 = \_SB.GPC0 (Local2) + Local1 |= PAD_CFG0_TX_STATE \_SB.SPC0 (Local2, Local1) } @@ -151,9 +151,9 @@ * local1 - to toggle Tx pin of Dw0 * local2 - Address of PERST */ - Store (Arg0, Local2) - Store (\_SB.GPC0 (Local2), Local1) - And (Local1, Not (PAD_CFG0_TX_STATE), Local1) + Local2 = Arg0 + Local1 = \_SB.GPC0 (Local2) + Local1 &= ~PAD_CFG0_TX_STATE \_SB.SPC0 (Local2, Local1) } } diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl index 31599f2..a9c0b12 100644 --- a/src/soc/intel/apollolake/acpi/gpiolib.asl +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -6,7 +6,7 @@ Method (GPC0, 0x1, Serialized) { /* Arg0 - GPIO DW0 address */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (PDW0, SystemMemory, Local0, 4) Field (PDW0, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -19,19 +19,19 @@ { /* Arg0 - GPIO DW0 address */ /* Arg1 - Value for DW0 register */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (PDW0, SystemMemory, Local0, 4) Field (PDW0, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 } /* Get Pad Configuration DW1 register value */ Method (GPC1, 0x1, Serialized) { /* Arg0 - GPIO DW0 address */ - Store (Arg0 + 4, Local0) + Local0 = Arg0 + 4 OperationRegion (PDW1, SystemMemory, Local0, 4) Field (PDW1, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -44,12 +44,12 @@ { /* Arg0 - GPIO DW0 address */ /* Arg1 - Value for DW1 register */ - Store (Arg0 + 4, Local0) + Local0 = Arg0 + 4 OperationRegion (PDW1, SystemMemory, Local0, 4) Field(PDW1, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 } /* Get DW0 address of a given pad */ @@ -57,10 +57,9 @@ { /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ - Store (0, Local1) - Or( Or (ShiftLeft (Arg0, 16), CONFIG_PCR_BASE_ADDRESS), - Local1, Local1) - Or(PAD_CFG_BASE + Arg1 * GPIO_NUM_PAD_CFG_REGS * 4, Local1, Local1) + Local1 = 0 + Local1 |= (Arg0 << 16) | CONFIG_PCR_BASE_ADDRESS + Local1 |= (PAD_CFG_BASE + Arg1 * GPIO_NUM_PAD_CFG_REGS * 4) Return (Local1) } @@ -77,10 +76,9 @@ { /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ - Store (CHSA (Arg1), Local1) - OperationRegion (SHO0, SystemMemory, Or ( Or - (CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4) + OperationRegion (SHO0, SystemMemory, CONFIG_PCR_BASE_ADDRESS | + (Arg0 << 16) | CHSA (Arg1), 4) Field (SHO0, AnyAcc, NoLock, Preserve) { TEMP, 32 } @@ -93,13 +91,12 @@ /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ /* Arg2 - Value for Host own register */ - Store (CHSA (Arg1), Local1) - OperationRegion (SHO0, SystemMemory, Or ( Or - (CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4) + OperationRegion (SHO0, SystemMemory, CONFIG_PCR_BASE_ADDRESS | + (Arg0 << 16) | CHSA (Arg1), 4) Field (SHO0, AnyAcc, NoLock, Preserve) { TEMP, 32 } - Store (Arg2, TEMP) + TEMP = Arg2 } } diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 6791e15..834e5e4 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -78,9 +78,9 @@ CreateDwordField (MCRS, PM01._LEN, PLEN) /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, PMIN) + PMIN = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 /* Read MMCONF base */ - And(\_SB.PCI0.MCHC.MCNF, 0xF0000000, PMAX) + PMAX = \_SB.PCI0.MCHC.MCNF & 0xF0000000 /* Calculate PCI MMIO Length */ PLEN = PMAX - PMIN + 1 @@ -91,24 +91,24 @@ CreateDwordField(MCRS, STOM._LEN, GLEN) /* Read BGSM */ - And(\_SB.PCI0.MCHC.BGSM, 0xFFF00000, GMIN) + GMIN = \_SB.PCI0.MCHC.BGSM & 0xFFF00000 /* Read TOLUD */ - And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, GMAX) + GMAX = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 GMAX-- GLEN = GMAX - GMIN + 1 /* Patch PM02 range based on Memory Size */ - If (LEqual (A4GS, 0)) { + If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) - Store (0, MSEN) + MSEN = 0 } Else { CreateQwordField (MCRS, PM02._MIN, MMIN) CreateQwordField (MCRS, PM02._MAX, MMAX) CreateQwordField (MCRS, PM02._LEN, MLEN) /* Set 64bit MMIO resource base and length */ - Store (A4GS, MLEN) - Store (A4GB, MMIN) + MLEN = A4GS + MMIN = A4GB MMAX = MMIN + MLEN - 1 } diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl index 6c9a14a..1b595e9 100644 --- a/src/soc/intel/apollolake/acpi/pch_hda.asl +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -29,17 +29,17 @@ * Arg2 - Function Index */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LEqual (Arg1, One) && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) { + If (Arg1 == 1 && NHLA != 0 && NHLL != 0) { Return (Buffer (One) { 0x03 }) } Else { @@ -54,13 +54,13 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } } diff --git a/src/soc/intel/apollolake/acpi/pcie_port.asl b/src/soc/intel/apollolake/acpi/pcie_port.asl index 34e2a73..f138271 100644 --- a/src/soc/intel/apollolake/acpi/pcie_port.asl +++ b/src/soc/intel/apollolake/acpi/pcie_port.asl @@ -39,8 +39,8 @@ /* Define the PowerResource for PCIe slot */ Method (_STA, 0, Serialized) { - Store (PDS, PDST) - If (LEqual (PDS, 1)) { + PDST = PDS + If (PDS == 1) { Return (0xf) } Else { Return (0) @@ -49,7 +49,7 @@ Method (_ON, 0, Serialized) { - If (LEqual (PDST, 1) && LNotEqual (\PRT0, 0)) { + If (PDST == 1 && \PRT0 != 0) { /* Enter this condition if device * is connected */ @@ -57,21 +57,21 @@ /* De-assert PERST */ \_SB.PCI0.PRDA (\PRT0) - Store (0, BDQA) /* Set BLKDQDA to 0 */ - Store (0, BPLL) /* Set BLKPLLEN to 0 */ + BDQA = 0 /* Set BLKDQDA to 0 */ + BPLL = 0 /* Set BLKPLLEN to 0 */ /* Set L23_Rdy to Detect Transition * (L23R2DT) */ - Store (1, L23R) + L23R = 1 Sleep (16) - Store (0, Local0) + Local0 = 0 /* Delay for transition Detect * and link to train */ While (L23R) { - If (Lgreater (Local0, 4)) { + If (Local0 > 4) { Break } Sleep (16) @@ -83,22 +83,22 @@ Method (_OFF, 0, Serialized) { /* Set L23_Rdy Entry Request (L23ER) */ - If (LEqual (PDST, 1) && LNotEqual (\PRT0, 0)) { + If (PDST == 1 && \PRT0 != 0) { /* enter this condition if device * is connected */ - Store (1, L23E) + L23E = 1 Sleep (16) - Store (0, Local0) + Local0 = 0 While (L23E) { - If (Lgreater (Local0, 4)) { + If (Local0 > 4) { Break } Sleep (16) Local0++ } - Store (1, BDQA) /* Set BLKDQDA to 1 */ - Store (1, BPLL) /* Set BLKPLLEN to 1 */ + BDQA = 1 /* Set BLKDQDA to 1 */ + BPLL = 1 /* Set BLKPLLEN to 1 */ /* Assert PERST */ \_SB.PCI0.PRAS (\PRT0) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index b41a21a..d90b42e 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -30,15 +30,15 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) - Store (PCH_PWRM_BASE_ADDRESS, IBAS) + IBAS = PCH_PWRM_BASE_ADDRESS CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) - Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) + MDBA = MCH_BASE_ADDRESS + MAILBOX_DATA CreateDwordField (^RBUF, ^MINF._BAS, MIBA) - Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) + MIBA = MCH_BASE_ADDRESS + MAILBOX_INTF CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) - Store (SRAM_BASE_0, SBAS) + SBAS = SRAM_BASE_0 Return (^RBUF) } diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index a5a1f06..9a2ccd5 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -4,8 +4,7 @@ /* 0xD6- is the port address */ /* 0x600- is the dynamic clock gating control register offset (GENR) */ OperationRegion (SBMM, SystemMemory, - Or ( Or (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18) + CONFIG_PCR_BASE_ADDRESS | (0xD6 << PCR_PORTID_SHIFT) | 0x0600, 0x18) Field (SBMM, DWordAcc, NoLock, Preserve) { GENR, 32, @@ -23,10 +22,10 @@ */ Method (SCPG, 2, Serialized) { - if (LEqual(Arg0, 0x1)) { - Or (^GENR, Arg1, ^GENR) - } ElseIf (LEqual(Arg0, 0x0)){ - And (^GENR, Arg1, ^GENR) + if (Arg0 == 1) { + ^GENR |= Arg1 + } ElseIf (Arg0 == 0) { + ^GENR &= Arg1 } } @@ -44,13 +43,13 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 9: Device Readiness Durations * Returns a package of five integers covering * various device related delays in PCIe Base Spec. */ - If (LEqual (Arg2, 9)) { + If (Arg2 == 9) { /* * Function 9 support for revision 3. * ECN link for function definitions @@ -58,7 +57,7 @@ * specification_documents/ * ECN_fw_latency_optimization_final.pdf] */ - If (LEqual (Arg1, 3)) { + If (Arg1 == 3) { /* * Integer 0: FW reset time. * Integer 1: FW data link up time. @@ -118,14 +117,14 @@ Method (_INI, 0) { /* Check SDCard CD port is valid */ - If (LNotEqual (\SCDP, 0) && LNotEqual (\SCDO, 0)) + If (\SCDP != 0 && \SCDO != 0) { /* Store DW0 address of SD_CD */ - Store (GDW0 (\SCDP, \SCDO), SCD0) + SCD0 = GDW0 (\SCDP, \SCDO) /* Get the current SD_CD ownership */ - Store (\_SB.GHO (\SCDP, \SCDO), Local0) + Local0 = \_SB.GHO (\SCDP, \SCDO) /* Set host ownership as GPIO in HOSTSW_OWN reg */ - Or (Local0, ShiftLeft (1, Mod (\SCDO, 32)), Local0) + Local0 |= 1 << (\SCDO % 32) \_SB.SHO (\SCDP, \SCDO, Local0) } } @@ -133,20 +132,20 @@ Method (_PS0, 0, NotSerialized) { /* Check SDCard CD port is valid */ - If (LNotEqual (\SCDP, 0) && LNotEqual (\SCDO, 0)) + If (\SCDP != 0 && \SCDO != 0) { /* Store DW0 into local0 to get rxstate of GPIO */ - Store (\_SB.GPC0 (SCD0), Local0) + Local0 = \_SB.GPC0 (SCD0) /* Extract rxstate [bit 1] of sdcard card detect pin */ - And (Local0, PAD_CFG0_RX_STATE, Local0) + Local0 &= PAD_CFG0_RX_STATE /* If the sdcard is present, rxstate is low. * If sdcard is not present, rxstate is High. * Write the inverted value of rxstate to GRR3. */ - If (LEqual (Local0, 0)) { - Store (1, ^^GRR3) + If (Local0 == 0) { + ^^GRR3 = 1 } Else { - Store (0, ^^GRR3) + ^^GRR3 = 0 } Sleep (2) } @@ -155,7 +154,7 @@ Method (_PS3, 0, NotSerialized) { /* Clear GRR3 to Power Gate SD Controller */ - Store (0, ^^GRR3) + ^^GRR3 = 0 } Device (CARD) -- To view, visit https://review.coreboot.org/c/coreboot/+/61243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb362b5be05421b6ad2b2a3126c2943b7d55d135 Gerrit-Change-Number: 61243 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61141 ) Change subject: mb/google/nissa: Add devicetree ...................................................................... mb/google/nissa: Add devicetree Fill in devicetree for nissa baseboard based on schematics. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61141 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb 1 file changed, 144 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Reka Norman: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index a5e2217..74b24c8 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -1,4 +1,148 @@ chip soc/intel/alderlake + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_H" + register "pmc_gpe0_dw2" = "GPP_F" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # S0ix enable + register "s0ix_enable" = "1" + + # Enable CNVi BT + register "CnviBtCore" = "true" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref tcss_xhci on end + device ref xhci on end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref heci1 on end + device ref emmc on end + device ref pcie_rp7 on + # Enable SD Card PCIE 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE7 SD card + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end end end 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 8 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/uart/uart8250reg.h: use shifts in constants
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61644 ) Change subject: drivers/uart/uart8250reg.h: use shifts in constants ...................................................................... drivers/uart/uart8250reg.h: use shifts in constants The UART8250_FCR_TRIGGER bits are bits 6 and 7 in the register, so rewrite the mask and constants as constants shifted by 6. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0663c1a641355b7bfb59f41479d17117178fb895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61644 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/drivers/uart/uart8250reg.h 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index 170c90e..35a6845 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -30,11 +30,11 @@ #define UART8250_FCR_CLEAR_RCVR BIT(1) /* Clear the RCVR FIFO */ #define UART8250_FCR_CLEAR_XMIT BIT(2) /* Clear the XMIT FIFO */ #define UART8250_FCR_DMA_SELECT BIT(3) /* For DMA applications */ -#define UART8250_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART8250_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART8250_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART8250_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART8250_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +#define UART8250_FCR_TRIGGER_MASK (3 << 6) /* Mask for the FIFO trigger range */ +#define UART8250_FCR_TRIGGER_1 (0 << 6) /* Mask for trigger set at 1 */ +#define UART8250_FCR_TRIGGER_4 (1 << 6) /* Mask for trigger set at 4 */ +#define UART8250_FCR_TRIGGER_8 (2 << 6) /* Mask for trigger set at 8 */ +#define UART8250_FCR_TRIGGER_14 (3 << 6) /* Mask for trigger set at 14 */ #define UART8250_LCR 0x03 #define UART8250_LCR_WLS_MSK 0x03 /* character length select mask */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0663c1a641355b7bfb59f41479d17117178fb895 Gerrit-Change-Number: 61644 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/uart/uart8250reg.h: use BIT() macro for bit definitions
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61643 ) Change subject: drivers/uart/uart8250reg.h: use BIT() macro for bit definitions ...................................................................... drivers/uart/uart8250reg.h: use BIT() macro for bit definitions Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib726dd77eaf1a4f8a7d9fbf8ab6d46a7bb1de6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61643 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/drivers/uart/uart8250reg.h 1 file changed, 37 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index 573eb6f..170c90e 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -3,16 +3,18 @@ #ifndef UART8250REG_H #define UART8250REG_H +#include <types.h> + /* Data */ #define UART8250_RBR 0x00 #define UART8250_TBR 0x00 /* Control */ #define UART8250_IER 0x01 -#define UART8250_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART8250_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART8250_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART8250_IER_RDI 0x01 /* Enable receiver data interrupt */ +#define UART8250_IER_MSI BIT(3) /* Enable Modem status interrupt */ +#define UART8250_IER_RLSI BIT(2) /* Enable receiver line status interrupt */ +#define UART8250_IER_THRI BIT(1) /* Enable Transmitter holding register int. */ +#define UART8250_IER_RDI BIT(0) /* Enable receiver data interrupt */ #define UART8250_IIR 0x02 #define UART8250_IIR_NO_INT 0x01 /* No interrupts pending */ @@ -24,10 +26,10 @@ #define UART8250_IIR_RLSI 0x06 /* Receiver line status interrupt */ #define UART8250_FCR 0x02 -#define UART8250_FCR_FIFO_EN 0x01 /* Fifo enable */ -#define UART8250_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART8250_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART8250_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART8250_FCR_FIFO_EN BIT(0) /* Fifo enable */ +#define UART8250_FCR_CLEAR_RCVR BIT(1) /* Clear the RCVR FIFO */ +#define UART8250_FCR_CLEAR_XMIT BIT(2) /* Clear the XMIT FIFO */ +#define UART8250_FCR_DMA_SELECT BIT(3) /* For DMA applications */ #define UART8250_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ #define UART8250_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ #define UART8250_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ @@ -40,19 +42,19 @@ #define UART8250_LCR_WLS_6 0x01 /* 6 bit character length */ #define UART8250_LCR_WLS_7 0x02 /* 7 bit character length */ #define UART8250_LCR_WLS_8 0x03 /* 8 bit character length */ -#define UART8250_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define UART8250_LCR_PEN 0x08 /* Parity enable */ -#define UART8250_LCR_EPS 0x10 /* Even Parity Select */ -#define UART8250_LCR_STKP 0x20 /* Stick Parity */ -#define UART8250_LCR_SBRK 0x40 /* Set Break */ -#define UART8250_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART8250_LCR_STB BIT(2) /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define UART8250_LCR_PEN BIT(3) /* Parity enable */ +#define UART8250_LCR_EPS BIT(4) /* Even Parity Select */ +#define UART8250_LCR_STKP BIT(5) /* Stick Parity */ +#define UART8250_LCR_SBRK BIT(6) /* Set Break */ +#define UART8250_LCR_DLAB BIT(7) /* Divisor latch access bit */ #define UART8250_MCR 0x04 -#define UART8250_MCR_DTR 0x01 /* DTR */ -#define UART8250_MCR_RTS 0x02 /* RTS */ -#define UART8250_MCR_OUT1 0x04 /* Out 1 */ -#define UART8250_MCR_OUT2 0x08 /* Out 2 */ -#define UART8250_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART8250_MCR_DTR BIT(0) /* DTR */ +#define UART8250_MCR_RTS BIT(1) /* RTS */ +#define UART8250_MCR_OUT1 BIT(2) /* Out 1 */ +#define UART8250_MCR_OUT2 BIT(3) /* Out 2 */ +#define UART8250_MCR_LOOP BIT(4) /* Enable loopback test mode */ #define UART8250_MCR_DMA_EN 0x04 #define UART8250_MCR_TX_DFR 0x08 @@ -62,24 +64,24 @@ /* Status */ #define UART8250_LSR 0x05 -#define UART8250_LSR_DR 0x01 /* Data ready */ -#define UART8250_LSR_OE 0x02 /* Overrun */ -#define UART8250_LSR_PE 0x04 /* Parity error */ -#define UART8250_LSR_FE 0x08 /* Framing error */ -#define UART8250_LSR_BI 0x10 /* Break */ -#define UART8250_LSR_THRE 0x20 /* Xmit holding register empty */ -#define UART8250_LSR_TEMT 0x40 /* Xmitter empty */ -#define UART8250_LSR_ERR 0x80 /* Error */ +#define UART8250_LSR_DR BIT(0) /* Data ready */ +#define UART8250_LSR_OE BIT(1) /* Overrun */ +#define UART8250_LSR_PE BIT(2) /* Parity error */ +#define UART8250_LSR_FE BIT(3) /* Framing error */ +#define UART8250_LSR_BI BIT(4) /* Break */ +#define UART8250_LSR_THRE BIT(5) /* Xmit holding register empty */ +#define UART8250_LSR_TEMT BIT(6) /* Xmitter empty */ +#define UART8250_LSR_ERR BIT(7) /* Error */ #define UART8250_MSR 0x06 -#define UART8250_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART8250_MSR_RI 0x40 /* Ring Indicator */ -#define UART8250_MSR_DSR 0x20 /* Data Set Ready */ -#define UART8250_MSR_CTS 0x10 /* Clear to Send */ -#define UART8250_MSR_DDCD 0x08 /* Delta DCD */ -#define UART8250_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART8250_MSR_DDSR 0x02 /* Delta DSR */ -#define UART8250_MSR_DCTS 0x01 /* Delta CTS */ +#define UART8250_MSR_DCD BIT(7) /* Data Carrier Detect */ +#define UART8250_MSR_RI BIT(6) /* Ring Indicator */ +#define UART8250_MSR_DSR BIT(5) /* Data Set Ready */ +#define UART8250_MSR_CTS BIT(4) /* Clear to Send */ +#define UART8250_MSR_DDCD BIT(3) /* Delta DCD */ +#define UART8250_MSR_TERI BIT(2) /* Trailing edge ring indicator */ +#define UART8250_MSR_DDSR BIT(1) /* Delta DSR */ +#define UART8250_MSR_DCTS BIT(0) /* Delta CTS */ #define UART8250_SCR 0x07 #define UART8250_SPR 0x07 -- To view, visit https://review.coreboot.org/c/coreboot/+/61643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib726dd77eaf1a4f8a7d9fbf8ab6d46a7bb1de6c0 Gerrit-Change-Number: 61643 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/uart/uart8250reg.h: remove duplicate bit definitions
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61642 ) Change subject: drivers/uart/uart8250reg.h: remove duplicate bit definitions ...................................................................... drivers/uart/uart8250reg.h: remove duplicate bit definitions UART8250_FCR_RXSR is a redefinition of UART8250_FCR_CLEAR_RCVR, UART8250_FCR_TXSR a redefinition of UART8250_FCR_CLEAR_XMIT and UART8250_LCR_BKSE a redefinition of UART8250_LCR_DLAB. None of those redefinitions are used, so just drop them. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6b9edae67180b04ff1c887c5742c07c774fc9c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61642 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/drivers/uart/uart8250reg.h 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index 28dc21c..573eb6f 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -34,9 +34,6 @@ #define UART8250_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ #define UART8250_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ -#define UART8250_FCR_RXSR 0x02 /* Receiver soft reset */ -#define UART8250_FCR_TXSR 0x04 /* Transmitter soft reset */ - #define UART8250_LCR 0x03 #define UART8250_LCR_WLS_MSK 0x03 /* character length select mask */ #define UART8250_LCR_WLS_5 0x00 /* 5 bit character length */ @@ -48,7 +45,6 @@ #define UART8250_LCR_EPS 0x10 /* Even Parity Select */ #define UART8250_LCR_STKP 0x20 /* Stick Parity */ #define UART8250_LCR_SBRK 0x40 /* Set Break */ -#define UART8250_LCR_BKSE 0x80 /* Bank select enable */ #define UART8250_LCR_DLAB 0x80 /* Divisor latch access bit */ #define UART8250_MCR 0x04 -- To view, visit https://review.coreboot.org/c/coreboot/+/61642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9edae67180b04ff1c887c5742c07c774fc9c59 Gerrit-Change-Number: 61642 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UART
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61641 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UART ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UART Sabrina is compatible with the common AMD UART block and also with the DRIVERS_UART_8250MEM_32 driver it selects. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61641 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 7f1f87c..43c96c0 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -70,7 +70,7 @@ select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/61641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f Gerrit-Change-Number: 61641 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2022