coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
by Tim Wawrzynczak (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, Sridhar Siricilla, Angel Pons, Werner Zeh, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 ) Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/61519/comment/cab8fdf6_dbfbce45 PS4, Line 199: : if (eop_sent) { : printk(BIOS_ERR, "EOP already sent\n"); : return; : } : > > I suggested adding this as there was a TODO comment, and I thought this would be better than nothi […] I'd say let's go with #2 right now, if there is concern about sending EOP more than once. I am worried a little about continually adding more HECI traffic -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 15:37:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payload/external/iPXE/Makefile: Clean up the repo before checking out
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Felix Singer, Martin Roth, Stefan Reinauer. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60007 ) Change subject: payload/external/iPXE/Makefile: Clean up the repo before checking out ...................................................................... Patch Set 3: (1 comment) File payloads/external/iPXE/Makefile: https://review.coreboot.org/c/coreboot/+/60007/comment/7bc8d260_20f371e0 PS2, Line 32: git checkout maste > Force would probably do the trick if this is acceptable. […] Changed to --force -- To view, visit https://review.coreboot.org/c/coreboot/+/60007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3cfbb4c74c6397b00463087aeac58efb2777bbe Gerrit-Change-Number: 60007 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 15:36:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61681 ) Change subject: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO ...................................................................... soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to configure the PCI MMCONF base address. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/61681/1 diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 43c96c0..239a0e8 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -59,7 +59,7 @@ select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/61681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 Gerrit-Change-Number: 61681 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/pci/amd_pci_mmconf: add assert for MMCONF region
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61680 ) Change subject: soc/amd/common/block/pci/amd_pci_mmconf: add assert for MMCONF region ...................................................................... soc/amd/common/block/pci/amd_pci_mmconf: add assert for MMCONF region Add an assert that CONFIG_ECAM_MMCONF_BASE_ADDRESS only has bits set in the lower 32 bits. The current code assumes that it doesn't have any higher bits set and that it will always be below the 4GB boundary. This is not a hardware limitation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib0b4443d7a86f20c4c2508a88db5d731560f8312 --- M src/soc/amd/common/block/pci/amd_pci_mmconf.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61680/1 diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c index fb4db39..0296199 100644 --- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/amd_pci_mmconf.h> +#include <assert.h> #include <cpu/amd/msr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -9,6 +10,10 @@ { msr_t mmconf; + /* The hardware supports having the PCI MMCONF base address above 4GB, but 32 bit + coreboot doesn't. */ + _Static_assert(((uint64_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS >> 32) == 0, + "PCI MMCONF base is above 4GB."); mmconf.hi = 0; mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN | fms(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; -- To view, visit https://review.coreboot.org/c/coreboot/+/61680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0b4443d7a86f20c4c2508a88db5d731560f8312 Gerrit-Change-Number: 61680 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: payload/external/iPXE/Makefile: Clean up the repo before checking out
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Felix Singer, Martin Roth, Stefan Reinauer. Hello Felix Singer, build bot (Jenkins), Martin Roth, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60007 to look at the new patch set (#3). Change subject: payload/external/iPXE/Makefile: Clean up the repo before checking out ...................................................................... payload/external/iPXE/Makefile: Clean up the repo before checking out The iPXE file src/config/general.h is being modified when built for the first time due to various options like HAS_SCRIPT,PXE_NO_PROMPT or PXE_HAS_HTTPS. This leaves the repo in an unclean state and when rebuilt git yields an error when checking out the master branch: error: Your local changes to the following files would be overwritten by checkout: src/config/general.h Please commit your changes or stash them before you switch branches. Aborting fatal: A branch named 'coreboot' already exists. Avoid the error by forcing master branch checkout. TEST=Build coreboot apu2 with iPXE, then change an arbitrary configuration option to trigger rebuild of payloads. iPXE is rebuild without issues. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If3cfbb4c74c6397b00463087aeac58efb2777bbe --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/60007/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3cfbb4c74c6397b00463087aeac58efb2777bbe Gerrit-Change-Number: 60007 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/pcie/generic: Add new pcie generic chip driver
by Tim Wawrzynczak (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, Angel Pons, Nick Vaccaro, HAOUAS Elyes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61627 ) Change subject: drivers/pcie/generic: Add new pcie generic chip driver ...................................................................... Patch Set 3: (3 comments) File src/drivers/pcie/generic/chip.h: https://review.coreboot.org/c/coreboot/+/61627/comment/f59fe89d_07a81c3a PS3, Line 5: > include stdbool. […] will add <types.h> File src/drivers/pcie/generic/generic.c: https://review.coreboot.org/c/coreboot/+/61627/comment/76952002_12edcf51 PS3, Line 20: !config > You also need to update this Done https://review.coreboot.org/c/coreboot/+/61627/comment/7c360537_139c329f PS3, Line 41: pci_rom_ssdt(dev); > This is skipped when `!config->is_untrusted`, is it intentional? Good catch, will move up -- To view, visit https://review.coreboot.org/c/coreboot/+/61627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf Gerrit-Change-Number: 61627 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 07 Feb 2022 15:34:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/generic: Add new pcie generic chip driver
by Tim Wawrzynczak (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Angel Pons, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61627 to look at the new patch set (#4). Change subject: drivers/pcie/generic: Add new pcie generic chip driver ...................................................................... drivers/pcie/generic: Add new pcie generic chip driver This new chip driver will be used for attaching ACPI properties to PCIe endpoints. The first property it supports is "UntrustedDevice." This property can be used by a payload to, e.g., restrict the device to its own IOMMU domain for security purposes. The new property is added by adding a _DSD and an integer property set to 1. Example of the property from google/brya0: Scope (\_SB.PCI0.RP01) { Device (DEV0) { Name (_ADR, 0x0000000000000000) // _ADR: Address Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "UntrustedDevice", One } } }) } } BUG=b:215424986 TEST=boot patch train on google/brya0, dump SSDT, see above for snippet Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf --- A src/drivers/pcie/generic/Kconfig A src/drivers/pcie/generic/Makefile.inc A src/drivers/pcie/generic/chip.h A src/drivers/pcie/generic/generic.c 4 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/61627/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf Gerrit-Change-Number: 61627 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Mark the WWAN device as an UntrustedDevice
by Tim Wawrzynczak (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61628 ) Change subject: mb/google/brya: Mark the WWAN device as an UntrustedDevice ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Should we put the in variant? Right now, this will automatically apply to all variants that enable RP6 for WWAN (and it will only take effect if there is a PCI device found downstream of RP6) -- To view, visit https://review.coreboot.org/c/coreboot/+/61628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e Gerrit-Change-Number: 61628 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 15:30:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Add stylus probe
by Tim Wawrzynczak (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Evan Green, SH Kim, Marco Chen, Tim Wawrzynczak, Edward Doan, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61618 ) Change subject: mb/google/dedede/var/bugzzy: Add stylus probe ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61618/comment/9678aab9_6e1a11a9 PS2, Line 12: TEST=non-stylus sku doesn't register garage driver `BRANCH=dedede` -- To view, visit https://review.coreboot.org/c/coreboot/+/61618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42a63976b9521844f64180b550b16bac344f37 Gerrit-Change-Number: 61618 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Edward Doan <edoan(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 15:27:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/apollolake: Hook up VTD to CMOS
by Sean Rhodes (Code Review) 07 Feb '22

07 Feb '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61679 ) Change subject: soc/apollolake: Hook up VTD to CMOS ...................................................................... soc/apollolake: Hook up VTD to CMOS Hook up vtd_enable to CMOS value of "vtd". Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c --- M src/soc/intel/apollolake/chip.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/61679/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 82ec2da..5440230 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -23,6 +23,7 @@ #include <intelblocks/gpio.h> #include <intelblocks/itss.h> #include <intelblocks/pmclib.h> +#include <option.h> #include <soc/cpu.h> #include <soc/heci.h> #include <soc/intel/common/vbt.h> @@ -687,7 +688,7 @@ silconfig->VmxEnable = CONFIG(ENABLE_VMX); /* Set VTD feature according to devicetree */ - silconfig->VtdEnable = cfg->enable_vtd; + silconfig->VtdEnable = get_uint_option("vtd", cfg->enable_vtd); silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); -- To view, visit https://review.coreboot.org/c/coreboot/+/61679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c Gerrit-Change-Number: 61679 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit February 2022