coreboot-gerrit February 2022

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Change in coreboot[master]: sb/intel/common/firmware: Hook up adding 10GbE LAN firmware
by Martin Roth (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Felix Singer, Jeff Daly, Paul Menzel, Patrick Rudolph. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60877 ) Change subject: sb/intel/common/firmware: Hook up adding 10GbE LAN firmware ...................................................................... Patch Set 13: (3 comments) File src/southbridge/intel/common/firmware/Kconfig: https://review.coreboot.org/c/coreboot/+/60877/comment/502b2a71_884f0365 PS13, Line 152: HAVE_ Usually the 'HAVE' options are more like what you use above - it usually signifies that a chipset supports an option, then can be enabled or disabled by another config option that uses a 'depends on' for the have option. Basically, I'm suggesting you swap the name of the two options. Not critical or a blocker, just the normal coreboot convention. (Yeah, that isn't documented anywhere - I guess I should do that.) https://review.coreboot.org/c/coreboot/+/60877/comment/3c196585_b3cd7f7c PS13, Line 170: HAVE_10GBE_1_BIN Obviously, same as above. File src/southbridge/intel/common/firmware/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60877/comment/b7718392_25bd6684 PS13, Line 89: Could you remove the newlines inside the target? We use newlines as breaks between targets, not internal to a target. -- To view, visit https://review.coreboot.org/c/coreboot/+/60877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id45ab4b69a85a5f8e52c0c4b130b6d729222b4c3 Gerrit-Change-Number: 60877 Gerrit-PatchSet: 13 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 17:20:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add `finalize` operation for CSE
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Add `finalize` operation for CSE ...................................................................... Patch Set 24: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60405/comment/512fa710_cceb1c4f PS19, Line 7: soc/intel/common/block/notify: Implement coreboot notify native driver > > Thanks for views.. my worry part is, if you switch off the FSP Notify code, and enables coreboot native code in this regard, then we might end-up loose changes if SOC team adds in the FSP notify API though the changes are optional. My concern is with respect to maintenance. > > Valid concern and we can have few strategies to ensure robustness > > 1. Refer to the SoC platform FAS security chapter and implement those recommended programming (ideally those are meant for OEM/ODM to implement, all IBVs do refer to the same document). > > 2. Intel can own this piece like what is being done YoY for Cache-as-RAM native code in `soc/intel/common/block/cpu/car`, eNEM as replacement for FSP-T for each SoC program. (on ADL it took several months to validate eNEM and enable finally) In the past we didn't pick FSP-T just to avoid extra enabling time for CAR/eNEM, right? > > Please share your thoughts on this. Ping! @Sridhar? Do you have some concern or we can mark this closed ? File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/60405/comment/8a39d957_932f4a36 PS24, Line 1195: static void cse_final(struct device *dev) : { : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) { : cse_send_end_of_post(); : : cse_control_global_reset_lock(); : : if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) { : cse_set_to_d0i3(); : heci1_disable(); : } : } : : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) : heci_set_to_d0i3(); : } > What if we aggregate both operations covered by SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT & SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE under single macro (like CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH?)? Few thoughts: 1. Additional maintenance of adding new Kconfig CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH and doing forward who enables it? 2. Having separate operation under specific Kconfig would make these operations still in context of FSP i.e. a SoC user feel free to pick, skip FSP notify 2a (ready to boot) but let FSP to perform 2b (end of firmware). combing under bigger umbrella would take away the freedom. 3. From SoC recommendation side, Ready to Boot and End of Post are event which has meaning and silicon prefer to perform some operation under specific hoods, hence, coreboot would allow the same flexibility for SoC vendor enggs to add the required code inside specific `if` clause without mixing it. -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 24 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 17:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Arthur Heymans. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Created CB:61682 to address the post-merge comments -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 07 Feb 2022 17:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/common: Move RAM calcualtion to common code
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61682 ) Change subject: nb/amd/common: Move RAM calcualtion to common code ...................................................................... nb/amd/common: Move RAM calcualtion to common code This patch addresses post-merge comments from CB:52922. This change only unifies the code used by AMD northbirdges. TEST=Boot PC Engines apu1 and see that RAM resources did not change. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3d222f6cbd26fe78d968d2883984f25e8b62ab5c --- M src/northbridge/amd/agesa/Makefile.inc M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c A src/northbridge/amd/common/Makefile.inc A src/northbridge/amd/common/ram_calc.c M src/northbridge/amd/nb_common.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc 9 files changed, 96 insertions(+), 137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/61682/1 diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index ca9096c..11ec9a2 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) +subdirs-y += ../common subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4b4ab67..e4cd187 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -104,33 +104,6 @@ } } -static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) -{ - u32 temp; - - if (fx_devs == 0) - get_fx_devs(); - - - temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] - if (!(temp & 1)) - return 0; // this memory range is not enabled - /* - * BKDG: {DramBase[35:24], 00_0000h} <= address[35:0] so shift left by 8 bits - * for physical address and the convert to KiB by shifting 10 bits left - */ - *basek = ((temp & 0x0fff0000)) >> (10 - 8); - /* - * BKDG address[35:0] <= {DramLimit[35:24], FF_FFFFh} converted as above but - * ORed with 0xffff to get real limit before shifting. - */ - temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] - *limitk = ((temp & 0x0fff0000) | 0xffff) >> (10 - 8); - *limitk += 1; // round up last byte - - return 1; -} - static u32 amdfam14_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -309,10 +282,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - resource_t basek, limitk; + u64 basek, limitk; u32 hole; - if (get_dram_base_limit(0, &basek, &limitk)) { + if (get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) { hole = pci_read_config32(__f1_dev[0], 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; @@ -513,6 +486,9 @@ u32 reset_memhole = 1; #endif + if (fx_devs == 0) + get_fx_devs(); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); @@ -546,9 +522,9 @@ #endif idx = 0x10; - resource_t basek, limitk, sizek; // 4 1T + u64 basek, limitk, sizek; // 4 1T - if (get_dram_base_limit(0, &basek, &limitk)) { + if (get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) { sizek = limitk - basek; printk(BIOS_DEBUG, "adsr: basek = %llx, limitk = %llx, sizek = %llx.\n", diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index bd0a5c8..2d7e93b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -102,39 +102,6 @@ } } -static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) -{ - u32 temp; - - if (fx_devs == 0) - get_fx_devs(); - - - temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] - if (!(temp & 1)) - return 0; // this memory range is not enabled - /* - * BKDG: {DramBase[47:24], 00_0000h} <= address[47:0] so shift left by 8 bits - * for physical address and the convert to KiB by shifting 10 bits left - */ - *basek = ((temp & 0xffff0000)) >> (10 - 8); - /* Now high bits [47:40] */ - temp = pci_read_config32(__f1_dev[nodeid], 0x140 + (nodeid << 3)); //[47:40] at [7:0] - *basek = *basek | ((resource_t)temp << (40 - 10)); - /* - * BKDG address[39:0] <= {DramLimit[47:24], FF_FFFFh} converted as above but - * ORed with 0xffff to get real limit before shifting. - */ - temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] - *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); - /* Now high bits [47:40] */ - temp = pci_read_config32(__f1_dev[nodeid], 0x144 + (nodeid << 3)); //[47:40] at [7:0] - *limitk = *limitk | ((resource_t)temp << (40 - 10)); - *limitk += 1; // round up last byte - - return 1; -} - static u32 amdfam15_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -626,9 +593,9 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - resource_t basek, limitk; + u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole @@ -644,8 +611,8 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - resource_t base_k, limit_k; - if (!get_dram_base_limit(i, &base_k, &limit_k)) + u64 base_k, limit_k; + if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -671,6 +638,9 @@ u32 reset_memhole = 1; #endif + if (fx_devs == 0) + get_fx_devs(); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -705,9 +675,9 @@ idx = 0x10; for (i = 0; i < node_nums; i++) { - resource_t basek, limitk, sizek; // 4 1T + u64 basek, limitk, sizek; // 4 1T - if (!get_dram_base_limit(i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 3d5313a..e754f99 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -102,33 +102,6 @@ } } -static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) -{ - u32 temp; - - if (fx_devs == 0) - get_fx_devs(); - - - temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] - if (!(temp & 1)) - return 0; // this memory range is not enabled - /* - * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits - * for physical address and the convert to KiB by shifting 10 bits left - */ - *basek = ((temp & 0xffff0000)) >> (10 - 8); - /* - * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but - * ORed with 0xffff to get real limit before shifting. - */ - temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] - *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); - *limitk += 1; // round up last byte - - return 1; -} - static u32 amdfam16_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -638,9 +611,9 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - resource_t basek, limitk; + u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole @@ -656,8 +629,8 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - resource_t base_k, limit_k; - if (!get_dram_base_limit(i, &base_k, &limit_k)) + u64 base_k, limit_k; + if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -683,6 +656,9 @@ u32 reset_memhole = 1; #endif + if (fx_devs == 0) + get_fx_devs(); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -719,7 +695,7 @@ for (i = 0; i < node_nums; i++) { resource_t basek, limitk, sizek; // 4 1T - if (!get_dram_base_limit(i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/common/Makefile.inc b/src/northbridge/amd/common/Makefile.inc new file mode 100644 index 0000000..ee5d69d --- /dev/null +++ b/src/northbridge/amd/common/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += ram_calc.c diff --git a/src/northbridge/amd/common/ram_calc.c b/src/northbridge/amd/common/ram_calc.c new file mode 100644 index 0000000..259554e --- /dev/null +++ b/src/northbridge/amd/common/ram_calc.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <commonlib/bsd/helpers.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <northbridge/amd/nb_common.h> + +int get_dram_base_limit(struct device *f1_dev, u32 nodeid, u64 *basek, u64 *limitk) +{ + u64 temp; + u32 address_bits = cpu_phys_address_size(); /* N bits of phys space */ + u64 address_mask = (1ULL << address_bits) - 1; + + if (!f1_dev) { + printk(BIOS_ERR, "Northbridge function 1 not found\n"); + return 0; + } + + /* BKDG: {DramBase[N-1:24], 00_0000h} <= address[N:0] */ + temp = pci_read_config32(f1_dev, 0x40 + (nodeid << 3)); + if (!(temp & 1)) + return 0; /* this memory range is not enabled */ + /* [N-1:24] at [N-1-8:16], if N < 40 addres_mask will clear unused high bits */ + *basek = ((temp & 0xffff0000) << 8) & address_mask; + + if (address_bits > 40) { + /* [N-1:40] at [N-1-40:0], addres_mask will clear unused high bits */ + temp = pci_read_config32(f1_dev, 0x140 + (nodeid << 3)); + *basek |= ((temp << 40) & address_mask); + } + + *basek /= KiB; /* Normalize to KiB */ + + /* + * BKDG address[N-1:0] <= {DramLimit[N-1:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit + */ + /* [N-1:24] at [N-1-8:16], if N < 40 addres_mask will clear unused high bits */ + temp = pci_read_config32(f1_dev, 0x44 + (nodeid << 3)); + *limitk = ((temp << 8) | 0xffffff) & address_mask; + + if (address_bits > 40) { + /* [N-1:40] at [N-1-40:0] addres_mask will clear unused high bits */ + temp = pci_read_config32(f1_dev, 0x144 + (nodeid << 3)); + *limitk |= ((temp << 40) & address_mask); + } + + *limitk += 1; /* round up last byte for northbridge resource calculation convenience */ + *limitk /= KiB; /* Normalize to KiB */ + + return 1; +} diff --git a/src/northbridge/amd/nb_common.h b/src/northbridge/amd/nb_common.h index bee75c7..c6515c8 100644 --- a/src/northbridge/amd/nb_common.h +++ b/src/northbridge/amd/nb_common.h @@ -9,4 +9,6 @@ #define DEV_CDB 0x18 #define IO_APIC2_ADDR 0xfec20000 +int get_dram_base_limit(struct device *f1_dev, u32 nodeid, u64 *basek, u64 *limitk); + #endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 42505ab..6bc313d 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -88,33 +88,6 @@ } } -static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) -{ - u32 temp; - - if (fx_devs == 0) - get_fx_devs(); - - - temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] - if (!(temp & 1)) - return 0; // this memory range is not enabled - /* - * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits - * for physical address and the convert to KiB by shifting 10 bits left - */ - *basek = ((temp & 0xffff0000)) >> (10 - 8); - /* - * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but - * ORed with 0xffff to get real limit before shifting. - */ - temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] - *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); - *limitk += 1; // round up last byte - - return 1; -} - static u32 amdfam16_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -149,8 +122,8 @@ /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ - resource_t basek, limitk; - if (!get_dram_base_limit(0, &basek, &limitk)) + u64 basek, limitk; + if (!get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) return; mmio_resource(dev, index++, limitk, 16*1024); } @@ -743,9 +716,9 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < get_node_nums(); i++) { - resource_t basek, limitk; + u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole @@ -761,8 +734,8 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < get_node_nums(); i++) { - resource_t base_k, limit_k; - if (!get_dram_base_limit(i, &base_k, &limit_k)) + u64 base_k, limit_k; + if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -785,6 +758,9 @@ struct hw_mem_hole_info mem_hole; #endif + if (fx_devs == 0) + get_fx_devs(); + pci_domain_read_resources(dev); /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ @@ -807,9 +783,9 @@ idx = 0x10; for (i = 0; i < get_node_nums(); i++) { - resource_t basek, limitk, sizek; // 4 1T + u64 basek, limitk, sizek; // 4 1T - if (!get_dram_base_limit(i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index f73b0d5..3a51bc7 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y) +subdirs-y += ../common subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/61682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d222f6cbd26fe78d968d2883984f25e8b62ab5c Gerrit-Change-Number: 61682 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Nico Huber, Michał Kopeć, Angel Pons, Felix Held. Hello build bot (Jenkins), Nico Huber, Michał Kopeć, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52935 to look at the new patch set (#7). Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... nb/amd/agesa/family14/northbridge.c: Report missing resources Not all resources were being reported, add them. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 49 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52935/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/agesa/family14: Enable PARALLEL_MP
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Michał Żygowski, Paul Menzel. Michał Żygowski has uploaded a new patch set (#8) to the change originally created by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/59807 ) Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP ...................................................................... nb/amd/agesa/family14: Enable PARALLEL_MP Disable LEGACY_SMP_INIT and enable PARALLEL_MP. TEST=Boot Debian 11 on PC Engines apu1 Boot time reduced by ~3ms on average. Inspired by CB:59693 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I39a0779bdf115eebe31290591152b920acde773e --- M src/cpu/amd/agesa/family14/model_14_init.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family14/northbridge.c 3 files changed, 23 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59807/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a0779bdf115eebe31290591152b920acde773e Gerrit-Change-Number: 59807 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Hello build bot (Jenkins), Michał Kopeć, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52781 to look at the new patch set (#8). Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution ...................................................................... cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution Create the correct MTRR solution based on the physical address space provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not account for lost C6 DRAM storage MTRR during postcar frame creation. The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and overlapping with usable DRAM WB MTRR. However this UC MTRR remained on APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR function to create correct MTRR solution that propagates to APs. This also fixes the inconsistent MTRRs warning. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/cpu/amd/agesa/family14/model_14_init.c 1 file changed, 33 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Gerrit-Change-Number: 52781 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/agesa/family14: Use generic allocation functions for PCI domain
by Michał Żygowski (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53954 to look at the new patch set (#6). Change subject: nb/amd/agesa/family14: Use generic allocation functions for PCI domain ...................................................................... nb/amd/agesa/family14: Use generic allocation functions for PCI domain Move the DRAM reporting to read_resoures function before the resources are being set. Use generic PCI domain resource allocation functions to read and set domain resources. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie322c7eee443646a5690920c1e06851ee5fdfac3 --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 5 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/53954/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/53954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie322c7eee443646a5690920c1e06851ee5fdfac3 Gerrit-Change-Number: 53954 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Matt DeVillier (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Sean Rhodes, Martin Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61620 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Patch Set 21: (8 comments) File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/61620/comment/1a0cbec6_028259d4 PS20, Line 5: $(obj) how does this resolve to payloads/external/tianocore/output ? https://review.coreboot.org/c/coreboot/+/61620/comment/5a7fae03_701ce88b PS20, Line 9: TIANOCORE_REPOSITORY worth adding 9elements and/or System76's repos (possibly in a follow-up commit)? https://review.coreboot.org/c/coreboot/+/61620/comment/3349b238_5d3b8236 PS20, Line 12: TIANOCORE_UPSTREAM should be TIANOCORE_COREBOOTPAYLOAD https://review.coreboot.org/c/coreboot/+/61620/comment/e730b052_77ae23f0 PS20, Line 113: config TIANOCORE_BOOT_MANAGER_ESCAPE : bool "Use Escape key for Boot Manager" : default n : help : Use Escape as the hot-key to access the Boot Manager. This replaces : the default key of F2. add this and other new Kconfig / build params in a follow-on commit? File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/61620/comment/88ab22d8_e6155223 PS20, Line 9: BUILD_STR = -q : BUILD_STR += -a IA32 -a X64 -t COREBOOT why set these on separate lines? Also, worth adding a toggle for the -q so compilation errors can be more easily debugged without manual editing? https://review.coreboot.org/c/coreboot/+/61620/comment/76e778de_68eebaed PS20, Line 22: # OPTION = DEFAULT_VALUE : # : # ABOVE_4G_MEMORY = TRUE : ifneq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y) : BUILD_STR += -D ABOVE_4G_MEMORY=FALSE : endif : # BOOTSPLASH_IMAGE = FALSE : ifneq ($(CONFIG_TIANOCORE_BOOTSPLASH_FILE),) : BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE : endif : # BOOT_MANAGER_ESCAPE = FALSE : ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE),y) : BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE : endif : # BUILD_TARGETS = RELEASE : ifeq ($(CONFIG_TIANOCORE_DEBUG),y) : BUILD_STR += -b DEBUG : endif : # FOLLOW_BGRT_SPEC = FALSE : ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y) : BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE : endif : # PS2_KEYBOARD_ENABLE = FALSE : ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y) : BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE : endif : # PLATFORM_BOOT_TIMEOUT = 3 : ifneq ($(TIANOCORE_BOOT_TIMEOUT),) : BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) : endif : # SIO_BUS_ENABLE = FALSE : ifeq ($(CONFIG_TIANOCORE_PS2_KEYBOARD),y) : BUILD_STR += -D SIO_BUS_ENABLE=TRUE : endif : # SHELL_TYPE = BUILD_SHELL : ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y) : BUILD_STR += -D SHELL_TYPE=NONE : endif : # USE_CBMEM_FOR_CONSOLE = FALSE : ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y) : BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE : endif I'm not sure leaving these unset for the default is ideal, since if the repo/branch being built from changes, the default could as well. I think it better that coreboot always explicitly set these. https://review.coreboot.org/c/coreboot/+/61620/comment/429a0648_fa3edb8f PS20, Line 146: */ > As it is now variable, if you change config's halfway through, the original directory wouldn't be re […] I'm good with it either way, but I'd lean towards distclean should remove everything not part of the coreboot repo (so keeping the change) File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/61620/comment/9ce2be52_32599f36 PS20, Line 84: depends on TIANOCORE_BOOTSPLASH_IMAGE separate commit since outside the scope of payloads/ ? -- To view, visit https://review.coreboot.org/c/coreboot/+/61620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Gerrit-Change-Number: 61620 Gerrit-PatchSet: 21 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 17:16:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL
by Paul Menzel (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Kane Chen, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61678 ) Change subject: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61678/comment/3431bc4a_48b92f7a PS1, Line 9: Max max https://review.coreboot.org/c/coreboot/+/61678/comment/54591a59_01c37116 PS1, Line 11: 1. Can this operating system control that mode too? 2. What do other platforms do? 3. On laptops is the energy efficient turbo preferred? -- To view, visit https://review.coreboot.org/c/coreboot/+/61678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafbe4ed2f732a0872197f870a82887a09d3043d Gerrit-Change-Number: 61678 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 17:08:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2022