coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

1 participants
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Change in coreboot[master]: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
by Bora Guvendik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Bora Guvendik, Selma Bensaid, Julius Werner, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59507 to look at the new patch set (#13). Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table ...................................................................... soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table Get boot performance timestamps from CSE and inject them into coreboot's timestamp table after normalizing to the zero-point value. BUG=b:182575295 TEST=Able to see TS elapse prior to IA reset on Brya/Redrix 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 88,000 945:CSE started to handle ICC configuration 88,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000) 0:1st timestamp 330,857 (48,857) 11:start of bootblock 341,811 (10,953) 12:end of bootblock 349,299 (7,487) Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/telemetry.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59507/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/59507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Gerrit-Change-Number: 59507 Gerrit-PatchSet: 13 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add custom PLD fields to devicetree for brya reference
by Won Chung (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, Benson Leung, Prashant Malani. Won Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61388 ) Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya reference ...................................................................... Patch Set 14: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61388/comment/8aaa64cf_881cc601 PS13, Line 7: mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es > reached > 72? […] Done Patchset: PS13: > Just curious, what this for? Hi EricR, We are trying to add more detailed PLD information to USB ports so that we can distinguish which one is the specific port at which physical location. For example, if there are one port on the left panel and one port on the right panel, we do not know which of C0 and C1 is the port on left vs right panel. By specifying physical location, we know what each specific physical port is doing. (e.g. power cable plugged to port C1 on the left side of the right panel) -- To view, visit https://review.coreboot.org/c/coreboot/+/61388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301 Gerrit-Change-Number: 61388 Gerrit-PatchSet: 14 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Benson Leung <bleung(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 18:17:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add custom PLD fields to devicetree for brya variants
by Won Chung (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, Nick Vaccaro, Benson Leung, Prashant Malani. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Benson Leung, Prashant Malani, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61571 to look at the new patch set (#5). Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya variants ...................................................................... mb/google/brya: Add custom PLD fields to devicetree for brya variants BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung(a)google.com> Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51 --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 11 files changed, 518 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/61571/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51 Gerrit-Change-Number: 61571 Gerrit-PatchSet: 5 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Benson Leung <bleung(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add custom PLD fields to devicetree for brya reference
by Won Chung (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Won Chung, Benson Leung, Prashant Malani. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Benson Leung, EricR Lai, Prashant Malani, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61388 to look at the new patch set (#14). Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya reference ...................................................................... mb/google/brya: Add custom PLD fields to devicetree for brya reference For USB ports, we want to use custom PLD fields with more details to indicate physical location. Custom PLD will also be added to other brya variants in the future as we figure out physical port locations on those devices. Type A port on MLB is removed since it is no longer used. BUG=b:216490477 TEST=emerge-brya coreboot & SSDT dump in Brya test device Signed-off-by: Won Chung <wonchung(a)google.com> Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301 --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya4es/overridetree.cb 2 files changed, 112 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61388/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/61388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301 Gerrit-Change-Number: 61388 Gerrit-PatchSet: 14 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Attention: Benson Leung <bleung(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Raul Rangel (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Robert Zieba, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Patch Set 15: (4 comments) File src/soc/amd/cezanne/fch.c: https://review.coreboot.org/c/coreboot/+/61259/comment/faff67f1_6e447fed PS15, Line 139: ) clang-format? https://review.coreboot.org/c/coreboot/+/61259/comment/2dfd10b3_e49f825f PS15, Line 148: printk nit: Add a return after the printk and drop the `} else {` block. This will save 1 level of indentation. https://review.coreboot.org/c/coreboot/+/61259/comment/3cb81139_722ebaea PS15, Line 180: && clang-format https://review.coreboot.org/c/coreboot/+/61259/comment/013dc9c2_d03f2f0a PS15, Line 210: const In theory you can drop the const here and modify the struct directly. -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 15 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Feb 2022 18:14:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Martin Roth, Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61620 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Patch Set 21: (7 comments) Patchset: PS21: b File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/61620/comment/70a653d6_6e7793d4 PS20, Line 5: $(obj) > how does this resolve to payloads/external/tianocore/output ? payloads/external/Makefile moves it from output - the double copy will be tidied up in a separate commit. https://review.coreboot.org/c/coreboot/+/61620/comment/67b5a446_9e47cdc4 PS20, Line 9: TIANOCORE_REPOSITORY > worth adding 9elements and/or System76's repos (possibly in a follow-up commit)? Maybe leave it up them if they want to? All it's doing is setting REPOSITORY and TAG_OR_REV accordingly, so it's not hard to do. https://review.coreboot.org/c/coreboot/+/61620/comment/24f82ad6_5e099c93 PS20, Line 12: TIANOCORE_UPSTREAM > should be TIANOCORE_COREBOOTPAYLOAD Done File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/61620/comment/6c265184_4be48b6a PS20, Line 9: BUILD_STR = -q : BUILD_STR += -a IA32 -a X64 -t COREBOOT > why set these on separate lines? Also, worth adding a toggle for the -q so compilation errors can be […] To make it easy to remove - how about we tie it to TIANOCORE_DEBUG, save another Kconfig option? https://review.coreboot.org/c/coreboot/+/61620/comment/84b40a01_0514c777 PS20, Line 22: # OPTION = DEFAULT_VALUE : # : # ABOVE_4G_MEMORY = TRUE : ifneq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y) : BUILD_STR += -D ABOVE_4G_MEMORY=FALSE : endif : # BOOTSPLASH_IMAGE = FALSE : ifneq ($(CONFIG_TIANOCORE_BOOTSPLASH_FILE),) : BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE : endif : # BOOT_MANAGER_ESCAPE = FALSE : ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE),y) : BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE : endif : # BUILD_TARGETS = RELEASE : ifeq ($(CONFIG_TIANOCORE_DEBUG),y) : BUILD_STR += -b DEBUG : endif : # FOLLOW_BGRT_SPEC = FALSE : ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y) : BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE : endif : # PS2_KEYBOARD_ENABLE = FALSE : ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y) : BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE : endif : # PLATFORM_BOOT_TIMEOUT = 3 : ifneq ($(TIANOCORE_BOOT_TIMEOUT),) : BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) : endif : # SIO_BUS_ENABLE = FALSE : ifeq ($(CONFIG_TIANOCORE_PS2_KEYBOARD),y) : BUILD_STR += -D SIO_BUS_ENABLE=TRUE : endif : # SHELL_TYPE = BUILD_SHELL : ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y) : BUILD_STR += -D SHELL_TYPE=NONE : endif : # USE_CBMEM_FOR_CONSOLE = FALSE : ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y) : BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE : endif > I'm not sure leaving these unset for the default is ideal, since if the repo/branch being built from […] I'd lean towards crossing that bridge if we ever need to - the build options "should" be identical for all repositories as hard coding stuff should really only be last resort or debugging. File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/61620/comment/a4b13334_58732925 PS20, Line 84: depends on TIANOCORE_BOOTSPLASH_IMAGE > separate commit since outside the scope of payloads/ ? Jenkins doesn't like it being left. -- To view, visit https://review.coreboot.org/c/coreboot/+/61620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Gerrit-Change-Number: 61620 Gerrit-PatchSet: 21 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 18:07:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Add support for PCIe Resizable BARs
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 ) Change subject: device: Add support for PCIe Resizable BARs ...................................................................... Patch Set 3: (1 comment) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/61215/comment/b1db26b0_45834844 PS2, Line 324: ctrl0 > This is the Resizable BAR Control Register for BAR 0; the field NBARs, although it is in the control […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Gerrit-Change-Number: 61215 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 18:02:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Add support for PCIe Resizable BARs
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 ) Change subject: device: Add support for PCIe Resizable BARs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Gerrit-Change-Number: 61215 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 18:02:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL
by Tim Wawrzynczak (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Kane Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61678 ) Change subject: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61678/comment/f1c37fd2_c0a18872 PS1, Line 12: intensiv `intensive` File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/61678/comment/836a56fc_495c6d83 PS1, Line 658: * Disable the energy efficient turbo mode */ : s_cfg->EnergyEfficientTurbo = 0; Looks like this is just setting a bit in MSR_POWER_CTL, could this just be moved to https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… here? and then set/disabled with a field in alderlake/chip.h ? Also what kind of power impact would this have in S0? -- To view, visit https://review.coreboot.org/c/coreboot/+/61678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafbe4ed2f732a0872197f870a82887a09d3043d Gerrit-Change-Number: 61678 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 17:58:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie: Moving EFS into FMAP section
by Raul Rangel (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61559 ) Change subject: mb/amd/chausie: Moving EFS into FMAP section ...................................................................... Patch Set 1: (1 comment) File src/mainboard/amd/chausie/board.fmd: https://review.coreboot.org/c/coreboot/+/61559/comment/f776a13a_21d7e02d PS1, Line 4: 3M Just FYI, we won't be able to use this on ChromeOS. The EFS header needs to be in the RO section. -- To view, visit https://review.coreboot.org/c/coreboot/+/61559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa9333f4097705a5c572756ac3ead3ae7a0b22a4 Gerrit-Change-Number: 61559 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 17:56:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2022