coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL
by Sridhar Siricilla (Code Review) 07 Feb '22

07 Feb '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61678 ) Change subject: soc/intel/alderlake: Disable Energy Efficient Turbo for ADL ...................................................................... soc/intel/alderlake: Disable Energy Efficient Turbo for ADL The patch disables Energy Efficient Turbo to allow CPU to reach Max. Turbo frequency. TEST=Build and run CPU intensiv workloads. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Iaafbe4ed2f732a0872197f870a82887a09d3043d --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/61678/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8aa20a8..90bccb3 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -654,8 +654,9 @@ s_cfg->Hwp = 1; s_cfg->Cx = 1; s_cfg->PsOnEnable = 1; - /* Enable the energy efficient turbo mode */ - s_cfg->EnergyEfficientTurbo = 1; + + /* Disable the energy efficient turbo mode */ + s_cfg->EnergyEfficientTurbo = 0; s_cfg->PkgCStateLimit = LIMIT_AUTO; /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafbe4ed2f732a0872197f870a82887a09d3043d Gerrit-Change-Number: 61678 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: Add loglevel prefix to interactive consoles
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61306 ) Change subject: console: Add loglevel prefix to interactive consoles ...................................................................... console: Add loglevel prefix to interactive consoles In an attempt to make loglevels more visible (and therefore useful, hopefully), this patch adds a prefix indicating the log level to every line sent to an "interactive" console (such as a UART). If the code contains a `printk(BIOS_DEBUG, "This is a debug message!\n"), it will now show up as [DEBUG] This is a debug message! on the UART output. "Stored" consoles (such as in CBMEM) will get a similar but more space-efficient feature in a later CL. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61306 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/commonlib/include/commonlib/loglevel.h M src/console/console.c M src/console/printk.c M src/include/console/streams.h 4 files changed, 70 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h index f268750..68b2285 100644 --- a/src/commonlib/include/commonlib/loglevel.h +++ b/src/commonlib/include/commonlib/loglevel.h @@ -157,4 +157,27 @@ #define BIOS_NEVER 9 /** @} */ +#ifndef __ASSEMBLER__ + +/* + * When printing logs, lines should be printed with the following prefixes in + * front of them according to the BIOS_LOG_PREFIX_PATTERN printf() pattern. + */ +#define BIOS_LOG_PREFIX_PATTERN "[%.5s] " +#define BIOS_LOG_PREFIX_MAX_LEVEL BIOS_SPEW +static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = { + /* Note: These strings are *not* null-terminated to save space. */ + [BIOS_EMERG] = "EMERG", + [BIOS_ALERT] = "ALERT", + [BIOS_CRIT] = "CRIT ", + [BIOS_ERR] = "ERROR", + [BIOS_WARNING] = "WARN ", + [BIOS_NOTICE] = "NOTE ", + [BIOS_INFO] = "INFO ", + [BIOS_DEBUG] = "DEBUG", + [BIOS_SPEW] = "SPEW ", +}; + +#endif /* __ASSEMBLER__ */ + #endif /* LOGLEVEL_H */ diff --git a/src/console/console.c b/src/console/console.c index 67da107..5b8a872 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -25,28 +25,35 @@ __system76_ec_init(); } -void console_tx_byte(unsigned char byte) +void console_interactive_tx_byte(unsigned char byte, void *data_unused) { - __cbmemc_tx_byte(byte); - __spkmodem_tx_byte(byte); - __qemu_debugcon_tx_byte(byte); - - /* Some consoles want newline conversion - * to keep terminals happy. - */ if (byte == '\n') { + /* Some consoles want newline conversion to keep terminals happy. */ __uart_tx_byte('\r'); __usb_tx_byte('\r'); } + __spkmodem_tx_byte(byte); + __qemu_debugcon_tx_byte(byte); __uart_tx_byte(byte); __ne2k_tx_byte(byte); __usb_tx_byte(byte); __spiconsole_tx_byte(byte); - __flashconsole_tx_byte(byte); __system76_ec_tx_byte(byte); } +void console_stored_tx_byte(unsigned char byte, void *data_unused) +{ + __flashconsole_tx_byte(byte); + __cbmemc_tx_byte(byte); +} + +void console_tx_byte(unsigned char byte) +{ + console_interactive_tx_byte(byte, NULL); + console_stored_tx_byte(byte, NULL); +} + void console_tx_flush(void) { __uart_tx_flush(); diff --git a/src/console/printk.c b/src/console/printk.c index ef3d29f..ddd14c0 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -67,9 +67,35 @@ }; }; +static void wrap_interactive_printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + vtxprintf(console_interactive_tx_byte, fmt, args, NULL); +} + +static void line_start(union log_state state) +{ + if (state.level > BIOS_LOG_PREFIX_MAX_LEVEL) + return; + if (state.speed == CONSOLE_LOG_FAST) + return; + + /* Interactive consoles get a `[DEBUG] ` style readable prefix. */ + wrap_interactive_printf(BIOS_LOG_PREFIX_PATTERN, bios_log_prefix[state.level]); +} + static void wrap_putchar(unsigned char byte, void *data) { union log_state state = { .as_ptr = data }; + static bool line_started = false; + + if (byte == '\n') { + line_started = false; + } else if (!line_started) { + line_start(state); + line_started = true; + } if (state.speed == CONSOLE_LOG_FAST) __cbmemc_tx_byte(byte); diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 44d96e2..f8b1216 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -10,6 +10,11 @@ void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* Interactive consoles that are usually displayed in real time on a terminal. */ +void console_interactive_tx_byte(unsigned char byte, void *data_unused); +/* Consoles that store logs on some medium for later retrieval. */ +void console_stored_tx_byte(unsigned char byte, void *data_unused); + /* * Write number_of_bytes data bytes from buffer to the serial device. * If number_of_bytes is zero, wait until all serial data is output. 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b Gerrit-Change-Number: 61306 Gerrit-PatchSet: 8 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add 5G WWAN ACPI support for Brya and Redrix
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61355 ) Change subject: mb/google/brya: Add 5G WWAN ACPI support for Brya and Redrix ...................................................................... mb/google/brya: Add 5G WWAN ACPI support for Brya and Redrix Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM features from RTD3. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61355 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 6 files changed, 47 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c0b8a34..386aa11 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -18,6 +18,7 @@ select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC + select DRIVERS_WWAN_FM350GL select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 7cc0204..a277120 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -154,8 +154,12 @@ # Enable WWAN PCIE 6 using clk 5 chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "reset_off_delay_ms" = "20" + register "reset_delay_ms" = "1000" register "srcclk_pin" = "5" - device generic 0 on end + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp6_rtd3 on end end register "pch_pcie_rp[PCH_RP(6)]" = "{ .clk_src = 5, diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 1ef90bc..c97ff33 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -192,6 +192,17 @@ end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end + end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index cae2257..59cd8c4 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -189,6 +189,16 @@ end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 0cb0102..0698568 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -167,6 +167,16 @@ end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 72f1da2..fc939c7 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -153,6 +153,16 @@ end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25 Gerrit-Change-Number: 61355 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support Support PXSX._RST and PXSX.MRST._RST for warm and cold reset. PXSX._RST is invoked on driver removal. build dependency: soc/intel/common/block/pcie/rtd3 This driver will use the rtd3 methods for the same parent in the device tree. The rtd3 chip needs to be added on the same root port in the devicetree separately. Test: Add chip entry to the corresponding root port and check PXSX Device is generated in ssdt. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61354 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/drivers/wwan/fm/Kconfig A src/drivers/wwan/fm/Makefile.inc A src/drivers/wwan/fm/acpi_fm350gl.c A src/drivers/wwan/fm/chip.h 4 files changed, 294 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/wwan/fm/Kconfig b/src/drivers/wwan/fm/Kconfig new file mode 100644 index 0000000..bed3b2e --- /dev/null +++ b/src/drivers/wwan/fm/Kconfig @@ -0,0 +1,11 @@ +config DRIVERS_WWAN_FM350GL + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 + help + This driver is for Fibocom FM350-GL PCIe 5G WWAN. + When enabled, this driver will add support for ACPI controlled + WWAN using GPIOs for power/reset control of the device. + This driver depends on rtd3 driver code to build as it needs to + point to the rtd3 chip on the same parent for the methods provided + only for the same root port. diff --git a/src/drivers/wwan/fm/Makefile.inc b/src/drivers/wwan/fm/Makefile.inc new file mode 100644 index 0000000..8074a08 --- /dev/null +++ b/src/drivers/wwan/fm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_WWAN_FM350GL) += acpi_fm350gl.c diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c new file mode 100644 index 0000000..15d0ecc --- /dev/null +++ b/src/drivers/wwan/fm/acpi_fm350gl.c @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include "chip.h" +#include "soc/intel/common/block/pcie/rtd3/chip.h" + +/* FCPO# to RESET# delay time during WWAN ON */ +#define FM350GL_TN2B 20 +/* RESET# to PERST# delay time during WWAN ON */ +#define FM350GL_TB2R 80 +/* The delay between de-assertion of PERST# to change of PDS state from 0 to 1 during WWAN ON */ +#define FM350GL_TR2P 0 +/* RESET# to FCPO# delay time during WWAN OFF */ +#define FM350GL_TB2F 10 +/* Time to allow the WWAN module to fully discharge any residual voltages before FCPO# could be + de-asserted again. */ +#define FM350GL_TFDI 500 +/* The delay between assertion and de-assertion RESET# during FLDR */ +#define FM350GL_TBTG 10 +/* The delay between de-assertion of RESET# and change of PDS state from 0 to 1 after FLDR */ +#define FM350GL_TBTP 170 +/* PERST# to RESET# delay time during WWAN OFF */ +#define FM350GL_TR2B 10 +/* 20s HW initialization needed after de-assertion of PERST# + However, it is not required and is not proper place to ensure HW initialization in ACPI. The + delay here is to ensure the following reset or RTD3 _OFF method won't be called immediately. + */ +#define FM350GL_TIME_HW_INIT 100 + +enum reset_type { + RESET_TYPE_WARM = 0, + RESET_TYPE_COLD = 1 +}; + +/* + * Returns the RTD3 PM methods requested and available to the device. + */ +static enum acpi_pcie_rp_pm_emit +wwan_fm350gl_get_rtd3_method_support(const struct drivers_wwan_fm_config *config) +{ + const struct soc_intel_common_block_pcie_rtd3_config *rtd3_config; + + rtd3_config = config_of(config->rtd3dev); + + return rtd3_config->ext_pm_support; +} + +/* + * Generate first half reset flow (FHRF) method. + * Arg0 = RESET_TYPE_WARM: warm reset + * Arg0 = 1RESET_TYPE_COLD: cold reset + */ +static void wwan_fm350gl_acpi_method_fhrf(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("FHRF", 1); + { + /* LOCAL0 = PERST# */ + acpigen_get_tx_gpio(&config->perst_gpio); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); + { + if (wwan_fm350gl_get_rtd3_method_support(config) | + ACPI_PCIE_RP_EMIT_L23) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "DL23")); + } + /* assert PERST# pin */ + acpigen_enable_tx_gpio(&config->perst_gpio); + } + acpigen_write_if_end(); /* If */ + acpigen_write_sleep(FM350GL_TR2B); + /* assert RESET# pin */ + acpigen_enable_tx_gpio(&config->reset_gpio); + /* warm reset */ + acpigen_write_if_lequal_op_int(ARG0_OP, RESET_TYPE_WARM); + { + acpigen_write_sleep(FM350GL_TBTG); + } + /* cold reset */ + acpigen_write_else(); + { + acpigen_write_if_lequal_op_int(ARG0_OP, RESET_TYPE_COLD); + { + /* disable source clock */ + if (wwan_fm350gl_get_rtd3_method_support(config) | + ACPI_PCIE_RP_EMIT_SRCK) { + acpigen_emit_namestring(acpi_device_path_join( + parent_dev, "SRCK")); + acpigen_emit_byte(ZERO_OP); + } + acpigen_write_sleep(FM350GL_TB2F); + /* assert FCPO# pin */ + acpigen_enable_tx_gpio(&config->fcpo_gpio); + acpigen_write_sleep(FM350GL_TFDI); + } + acpigen_write_if_end(); /* If */ + } + acpigen_pop_len(); /* Else */ + } + acpigen_write_method_end(); /* Method */ +} + +/* + * Generate second half reset flow (SHRF) method. + */ +static void wwan_fm350gl_acpi_method_shrf(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("SHRF", 0); + { + /* call rtd3 method to Disable ModPHY Power Gating. */ + if (wwan_fm350gl_get_rtd3_method_support(config) | + ACPI_PCIE_RP_EMIT_PSD0) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "PSD0")); + } + /* call rtd3 method to Enable SRC Clock. */ + if (wwan_fm350gl_get_rtd3_method_support(config) | + ACPI_PCIE_RP_EMIT_SRCK) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "SRCK")); + acpigen_emit_byte(ONE_OP); + } + /* De-assert FCPO# GPIO. */ + acpigen_disable_tx_gpio(&config->fcpo_gpio); + acpigen_write_sleep(FM350GL_TN2B); + /* De-assert RESET# GPIO. */ + acpigen_disable_tx_gpio(&config->reset_gpio); + acpigen_write_sleep(FM350GL_TB2R); + /* De-assert PERST# GPIO. */ + acpigen_disable_tx_gpio(&config->perst_gpio); + /* Call rtd3 method to trigger L2/L3 ready exit flow in root port */ + if (wwan_fm350gl_get_rtd3_method_support(config) | + ACPI_PCIE_RP_EMIT_L23) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "L23D")); + } + acpigen_write_sleep(FM350GL_TIME_HW_INIT); + } + acpigen_write_method_end(); /* Method */ +} + +/* + * Generate _RST method. This is to perform a soft reset. It is added under + * PXSX. This is called during device driver removal. + */ +static void wwan_fm350gl_acpi_method_rst(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("_RST", 0); + { + /* Perform 1st Half of FLDR Flow for soft reset: FHRF(0) */ + acpigen_emit_namestring("FHRF"); + acpigen_emit_byte(RESET_TYPE_WARM); + /* Perform 2nd Half of FLDR Flow: SHRF() */ + acpigen_emit_namestring("SHRF"); + /* Indicates that the following _Off will be skipped. */ + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "RTD3.OFSK")); + } + acpigen_write_method_end(); /* Method */ +} + +/* + * Generate _RST method. This is to perform a cold reset. This reset will be + * included under PXSX.MRST. This method is used during device firmware update. + */ +static void wwan_fm350gl_acpi_method_mrst_rst(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("_RST", 0); + { + /* Perform 1st Half of FLDR Flow for cold reset: FHRF (1) */ + acpigen_emit_namestring("FHRF"); + acpigen_emit_byte(RESET_TYPE_COLD); + /* Perform 2nd Half of FLDR Flow: SHRF () */ + acpigen_emit_namestring("SHRF"); + /* Indicate kernel ACPI PM to skip _off RTD3 after reset at the end of + driver removal */ + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "RTD3.OFSK")); + } + acpigen_write_method_end(); /* Method */ +} + +static const char *wwan_fm350gl_acpi_name(const struct device *dev) +{ + /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ + return "PXSX"; +} + +static void wwan_fm350gl_acpi_fill_ssdt(const struct device *dev) +{ + const struct drivers_wwan_fm_config *config = config_of(dev); + const struct device *parent = dev->bus->dev; + const char *scope = acpi_device_path(parent); + + if (!is_dev_enabled(parent)) { + printk(BIOS_ERR, "%s: root port not enabled\n", __func__); + return; + } + if (!scope) { + printk(BIOS_ERR, "%s: root port scope not found\n", __func__); + return; + } + if (!config->fcpo_gpio.pin_count && !config->reset_gpio.pin_count && + !config->perst_gpio.pin_count) { + printk(BIOS_ERR, "%s: FCPO, RESET, PERST GPIO required for %s.\n", + __func__, scope); + return; + } + printk(BIOS_INFO, "%s: Enable WWAN for %s (%s)\n", scope, dev_path(parent), + config->desc ?: dev->chip_ops->name); + acpigen_write_scope(scope); + { + acpigen_write_device(wwan_fm350gl_acpi_name(dev)); + { + acpigen_write_ADR(0); + if (config->name) + acpigen_write_name_string("_DDN", config->name); + if (config->desc) + acpigen_write_name_unicode("_STR", config->desc); + wwan_fm350gl_acpi_method_fhrf(parent, config); + wwan_fm350gl_acpi_method_shrf(parent, config); + wwan_fm350gl_acpi_method_rst(parent, config); + /* NOTE: the 5G driver will call MRST._RST to trigger a cold reset + * during firmware update. + */ + acpigen_write_device("MRST"); + { + acpigen_write_ADR(0); + wwan_fm350gl_acpi_method_mrst_rst(parent, config); + } + acpigen_write_device_end(); /* Device */ + } + acpigen_write_device_end(); /* Device */ + } + acpigen_write_scope_end(); /* Scope */ +} + +static struct device_operations wwan_fm350gl_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = wwan_fm350gl_acpi_fill_ssdt, + .acpi_name = wwan_fm350gl_acpi_name, +}; + +static void wwan_fm350gl_acpi_enable(struct device *dev) +{ + dev->ops = &wwan_fm350gl_ops; +} + +struct chip_operations drivers_wwan_fm_ops = { + CHIP_NAME("Fibocom FM-350-GL") + .enable_dev = wwan_fm350gl_acpi_enable +}; diff --git a/src/drivers/wwan/fm/chip.h b/src/drivers/wwan/fm/chip.h new file mode 100644 index 0000000..635178b --- /dev/null +++ b/src/drivers/wwan/fm/chip.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_WWAN_FM_CHIP_H__ +#define __DRIVERS_WWAN_FM_CHIP_H__ + +struct drivers_wwan_fm_config { + const char *name; + const char *desc; + /* GPIO used for FULL_CARD_POWER_OFF# */ + struct acpi_gpio fcpo_gpio; + + /* GPIO used for RESET# */ + struct acpi_gpio reset_gpio; + + /* GPIO used for PERST# */ + struct acpi_gpio perst_gpio; + + /* GPIO used for wake */ + struct acpi_gpio wake_gpio; + + /* Pointer to the corresponding RTD3 */ + DEVTREE_CONST struct device *rtd3dev; +}; + +#endif /* __DRIVERS_WWAN_FM_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 12 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61353 ) Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control ...................................................................... soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control - Optional feature to provide mechanism to skip _OFF and _On execution. - It is used for the device to skip _OFF and _ON during device driver reload. - OFSK is used to skip _OFF Method at the end of device driver removal. - ONSK is used to skip _ON Method at the beginning of driver loading. - General flow use case: 1. Device driver is removed by 'rmmod' command. 2. Device _RST is called. _RST perform reset. 3. Device increments OFSK in _RST to skip the following _OFF invoked by OSPM. 4. OSPM invokes _OFF at the end of driver removal. 5. _OFF sees OFSK and skips current execution and decrements OFSK so that _OFF will be executed normally next time. 6. _OFF increments ONSK to skip the following _ON invoked by OSPM. 7. Device driver is reloaded by 'insmod/modprobe' command. 8. OSPM invokes _ON at the beginning of driver loading. 9. _ON sees ONSK and skip current execution and decrements ONSK so that _ON will be executed normally next time. - In normal case: When suspend, OSPM invokes _OFF. Since OFSK is zero, the device goes to deeper state as expected. When resume, OSPM invokes _ON. Sinc ONSK is zero, the device goes to active state as expected. - Generated changes: PowerResource (RTD3, 0x00, 0x0000) Name (ONSK, Zero) Name (OFSK, Zero) ... Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { ... } Else { ONSK-- } } Method (_OFF, 0, Serialized) // _OFF: Power Off { If ((OFSK == Zero)) { ... } Else { OFSK-- ONSK++ } } Test: Enable and verify OFSK and ONSK Name objects and the if-condition logic inside _OFF and _ON methods is added. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61353 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 62 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h index 7541bc3..652aaff 100644 --- a/src/soc/intel/common/block/pcie/rtd3/chip.h +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -76,6 +76,12 @@ *-----------------------------------------------------------------------------------* */ enum acpi_pcie_rp_pm_emit ext_pm_support; + + /* + * Add support to skip _OFF and _ON execution when needed, such as reloading + * the device driver. + */ + bool skip_on_off_support; }; #endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 260aa65..8a9b068 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -147,6 +147,13 @@ { acpigen_write_method_serialized("_ON", 0); + /* When this feature is enabled, ONSK indicates if the previous _OFF was + * skipped. If so, since the device was not in Off state, and the current + * _ON can be skipped as well. + */ + if (config->skip_on_off_support) + acpigen_write_if_lequal_namestr_int("ONSK", 0); + /* Disable modPHY power gating for PCH RPs. */ if (rp_type == PCIE_RP_PCH) pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); @@ -173,6 +180,16 @@ if (!config->disable_l23) pcie_rtd3_acpi_l23_exit(); + if (config->skip_on_off_support) { + /* If current _ON is skipped, ONSK is decremented so that _ON will be + * executed normally until _OFF is skipped again. + */ + acpigen_write_else(); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_namestring("ONSK"); + + acpigen_pop_len(); /* Else */ + } acpigen_pop_len(); /* Method */ } @@ -183,6 +200,14 @@ { acpigen_write_method_serialized("_OFF", 0); + /* When this feature is enabled, ONSK is checked to see if the device + * wants _OFF to be skipped for once. ONSK is normally incremented in the + * device method, such as reset _RST, which is invoked during driver reload. + * In such case, _OFF needs to be avoided at the end of driver removal. + */ + if (config->skip_on_off_support) + acpigen_write_if_lequal_namestr_int("OFSK", 0); + /* Trigger L23 ready entry flow unless disabled by config. */ if (!config->disable_l23) pcie_rtd3_acpi_l23_entry(); @@ -209,6 +234,22 @@ acpigen_write_sleep(config->enable_off_delay_ms); } + if (config->skip_on_off_support) { + /* If current _OFF is skipped, ONSK is incremented so that the + * following _ON will also be skipped. In addition, OFSK is decremented + * so that next _OFF will be executed normally until the device method + * increments OFSK again. + */ + acpigen_write_else(); + /* OFSK-- */ + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_namestring("OFSK"); + /* ONSK++ */ + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring("ONSK"); + + acpigen_pop_len(); /* Else */ + } acpigen_pop_len(); /* Method */ } @@ -391,6 +432,21 @@ /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + if (config->skip_on_off_support) { + /* OFSK: 0 = _OFF Method will be executed normally when called; + * >1 = _OFF will be skipped. + * _OFF Method to decrement OFSK and increment ONSK if the + * current execution is skipped. + * ONSK: 0 = _ON Method will be executed normally when called; + * >1 = _ONF will be skipped. + * _ON Method to decrement ONSK if the current execution is + * skipped. + */ + acpigen_write_name_integer("ONSK", 0); + acpigen_write_name_integer("OFSK", 0); + } + pcie_rtd3_acpi_method_status(config); pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/61353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Gerrit-Change-Number: 61353 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61352 ) Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ...................................................................... soc/intel/common/block/pcie/rtd3: Add PM methods to the device. Add L23 enter/exit, modPHY power gate, and source clock control methods. DL23: method for L2/L3 entry. L23D: method for L2/L3 exit. PSD0: method for modPHY power gate. SRCK: method for enabling/disable source clock. These optional methods are to be used in the device ACPI to construct flows with root port's power management functions. Test: Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61352 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 100 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h index 15b8f64..7541bc3 100644 --- a/src/soc/intel/common/block/pcie/rtd3/chip.h +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -5,6 +5,17 @@ #include <acpi/acpi_device.h> +enum acpi_pcie_rp_pm_emit { + ACPI_PCIE_RP_EMIT_NONE = 0x00, /* None */ + ACPI_PCIE_RP_EMIT_L23 = 0x01, /* L23 */ + ACPI_PCIE_RP_EMIT_PSD0 = 0x02, /* PSD0 */ + ACPI_PCIE_RP_EMIT_SRCK = 0x04, /* SRCK */ + ACPI_PCIE_RP_EMIT_L23_PSD0 = 0x03, /* L23, PSD0 */ + ACPI_PCIE_RP_EMIT_L23_SRCK = 0x05, /* L23, SRCK */ + ACPI_PCIE_RP_EMIT_PSD0_SRCK = 0x06, /* PSD0, SRCK */ + ACPI_PCIE_RP_EMIT_ALL = 0x07 /* L23, PSD0, SRCK */ +}; + /* Device support at least one of enable/reset GPIO. */ struct soc_intel_common_block_pcie_rtd3_config { const char *desc; @@ -45,6 +56,26 @@ * Disable the ACPI-driven L23 Ready-to-Detect transition for the root port. */ bool disable_l23; + + /* + * Provides L23, modPHY gating, source clock enabling methods to the device + * connected root port, mainly used in the device ACPI methods such as reset. + * The methods to export are following this table: + *-----------------------------------------------------------------------------------* + | ext_pm_support | disable_l123 | srcclk_pin | rp_type | exported methods | + *----------------+--------------+------------+-------------+------------------------* + | false | - | - | - | None | + | true | true | =0 | PCIE_RP_CPU | None | + | true | true | =0 | PCIE_RP_PCH | SRCK | + | true | true | >0 | PCIE_RP_CPU | PSD0 | + | true | true | >0 | PCIE_RP_PCH | PSD0, SRCK | + | true | false | =0 | PCIE_RP_CPU | L23D, LD23 | + | true | false | =0 | PCIE_RP_PCH | L23D, LD23, SRCK | + | true | false | >0 | PCIE_RP_CPU | L23D, LD23, PSD0 | + | true | false | >0 | PCIE_RP_PCH | L23D, LD23, PSD0, SRCK | + *-----------------------------------------------------------------------------------* + */ + enum acpi_pcie_rp_pm_emit ext_pm_support; }; #endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 9f91d21..260aa65 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -100,6 +100,46 @@ acpigen_emit_namestring(RTD3_MUTEX_PATH); } +/* Method to enter L2/L3 */ +static void pcie_rtd3_acpi_method_dl23(void) +{ + acpigen_write_method_serialized("DL23", 0); + pcie_rtd3_acpi_l23_entry(); + acpigen_pop_len(); /* Method */ +} + +/* Method to exit L2/L3 */ +static void pcie_rtd3_acpi_method_l23d(void) +{ + acpigen_write_method_serialized("L23D", 0); + pcie_rtd3_acpi_l23_exit(); + acpigen_pop_len(); /* Method */ +} + +/* Method to disable PCH modPHY power gating */ +static void pcie_rtd3_acpi_method_pds0(unsigned int pcie_rp) +{ + acpigen_write_method_serialized("PSD0", 0); + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); + acpigen_pop_len(); /* Method */ +} + +/* Method to enable/disable the source clock */ +static void pcie_rtd3_acpi_method_srck(unsigned int pcie_rp, + const struct soc_intel_common_block_pcie_rtd3_config *config) +{ + acpigen_write_method_serialized("SRCK", 1); + + if (config->srcclk_pin >= 0) { + acpigen_write_if_lequal_op_op(ARG0_OP, 0); + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); + acpigen_write_else(); + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); + acpigen_pop_len(); /* If */ + } + acpigen_pop_len(); /* Method */ +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config, @@ -293,6 +333,24 @@ printk(BIOS_ERR, "%s: Unknown PCIe root port\n", __func__); return; } + if (config->disable_l23) { + if (config->ext_pm_support | ACPI_PCIE_RP_EMIT_L23) { + printk(BIOS_ERR, "%s: Can not export L23 methods\n", __func__); + return; + } + } + if (rp_type != PCIE_RP_PCH) { + if (config->ext_pm_support | ACPI_PCIE_RP_EMIT_PSD0) { + printk(BIOS_ERR, "%s: Can not export PSD0 method\n", __func__); + return; + } + } + if (config->srcclk_pin == 0) { + if (config->ext_pm_support | ACPI_PCIE_RP_EMIT_SRCK) { + printk(BIOS_ERR, "%s: Can not export SRCK method\n", __func__); + return; + } + } printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), config->desc ?: dev->chip_ops->name); @@ -316,10 +374,21 @@ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + if (config->ext_pm_support | ACPI_PCIE_RP_EMIT_L23) { + pcie_rtd3_acpi_method_dl23(); + pcie_rtd3_acpi_method_l23d(); + } + /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ if (rp_type == PCIE_RP_PCH) write_modphy_opregion(pcie_rp); + if (config->ext_pm_support | ACPI_PCIE_RP_EMIT_PSD0) + pcie_rtd3_acpi_method_pds0(pcie_rp); + + if (config->ext_pm_support | ACPI_PCIE_RP_EMIT_SRCK) + pcie_rtd3_acpi_method_srck(pcie_rp, config); + /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); pcie_rtd3_acpi_method_status(config); -- To view, visit https://review.coreboot.org/c/coreboot/+/61352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Gerrit-Change-Number: 61352 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools/spd_gen: Add support for Sabrina SoC
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61542 ) Change subject: util/spd_tools/spd_gen: Add support for Sabrina SoC ...................................................................... util/spd_tools/spd_gen: Add support for Sabrina SoC Add support to generate SPD binary for Sabrina SoC. Mainboards using Sabrina SoC are planning to use LP5 memory technology. Some of the SPD bytes expected by Sabrina differ from the existing ADL. To start with, memory training code for Sabrina expects SPD Revision 1.1. More patches will follow to accommodate additional differences. BUG=b:211510456 TEST=make -C util/spd_tools. Generate SPD binaries for the existing memory parts in lp5/memory_parts.json and observe that SPDs for Sabrina is generated as a separate set without impacting the ADL mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df Reviewed-on: https://review.coreboot.org/c/coreboot/+/61542 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M util/spd_tools/src/spd_gen/lp5.go M util/spd_tools/src/spd_gen/spd_gen.go 2 files changed, 32 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Reka Norman: Looks good to me, but someone else must approve diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go index 2e52bd5..22927b2 100644 --- a/util/spd_tools/src/spd_gen/lp5.go +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -55,6 +55,10 @@ getVal LP5SPDAttribFunc } +type LP5Set struct { + SPDRevision byte +} + /* ------------------------------------------------------------------------------------------ */ /* Constants */ /* ------------------------------------------------------------------------------------------ */ @@ -100,9 +104,13 @@ LP5SPDValueSize = 0x23 /* - * Revision 1.0. + * Revision 1.0. Expected by ADL */ - LP5SPDValueRevision = 0x10 + LP5SPDValueRevision1_0 = 0x10 + /* + * Revision 1.1. Expected by Sabrina + */ + LP5SPDValueRevision1_1 = 0x11 /* * As per advisory #616599, ADL MRC expects LPDDR5 memory type = 0x13. @@ -177,6 +185,16 @@ var LP5PlatformSetMap = map[int][]int{ 0: {PlatformADL}, + 1: {PlatformSBR}, +} + +var LP5SetInfo = map[int]LP5Set{ + 0: { + SPDRevision: LP5SPDValueRevision1_0, + }, + 1: { + SPDRevision: LP5SPDValueRevision1_1, + }, } var LP5PartAttributeMap = map[string]LP5MemAttributes{} @@ -280,7 +298,7 @@ var LP5SPDAttribTable = map[int]LP5SPDAttribTableEntry{ LP5SPDIndexSize: {constVal: LP5SPDValueSize}, - LP5SPDIndexRevision: {constVal: LP5SPDValueRevision}, + LP5SPDIndexRevision: {getVal: LP5EncodeSPDRevision}, LP5SPDIndexMemoryType: {constVal: LP5SPDValueMemoryType}, LP5SPDIndexModuleType: {constVal: LP5SPDValueModuleType}, LP5SPDIndexDensityBanks: {getVal: LP5EncodeDensityBanks}, @@ -309,6 +327,15 @@ /* ------------------------------------------------------------------------------------------ */ /* Functions */ /* ------------------------------------------------------------------------------------------ */ +func LP5EncodeSPDRevision(memAttribs *LP5MemAttributes) byte { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false { + return 0 + } + + return f.SPDRevision +} func LP5EncodeDensityBanks(memAttribs *LP5MemAttributes) byte { var b byte diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go index 6cc9102..9e939f0 100644 --- a/util/spd_tools/src/spd_gen/spd_gen.go +++ b/util/spd_tools/src/spd_gen/spd_gen.go @@ -72,6 +72,7 @@ PlatformJSL PlatformPCO PlatformCZN + PlatformSBR PlatformMax ) @@ -90,6 +91,7 @@ PlatformJSL: "JSL", PlatformPCO: "PCO", PlatformCZN: "CZN", + PlatformSBR: "SBR", } var memTechMap = map[string]memTech{ 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df Gerrit-Change-Number: 61542 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: adjust I2C3 speed
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61272 ) Change subject: mb/google/brya/var/kano: adjust I2C3 speed ...................................................................... mb/google/brya/var/kano: adjust I2C3 speed This change adjusts I2C3 speed to lower then 400KHz. BUG=b:215095284 BRANCH=None TEST=built and verified adjusted I2C3 speed < 400KHz Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ief6773bc37931a5393b5b1b8beaeda61d235f133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index c3b47fb..2121737 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -56,7 +56,7 @@ .data_hold_time_ns = 50, }, .i2c[3] = { - .speed = I2C_SPEED_FAST, + .speed = 390000, .rise_time_ns = 650, .fall_time_ns = 400, .data_hold_time_ns = 50, -- To view, visit https://review.coreboot.org/c/coreboot/+/61272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief6773bc37931a5393b5b1b8beaeda61d235f133 Gerrit-Change-Number: 61272 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/{taeko, taeko4es}: Configure Acoustic noise mitiga...
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61264 ) Change subject: mb/google/brya/var/{taeko, taeko4es}: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/{taeko, taeko4es}: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:201818726 TEST=build FW and system power on. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I881ded944530b21d1c5e306089d32387c9c258b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61264 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index f11da34..05eca50 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -39,6 +39,12 @@ end end chip soc/intel/alderlake + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index de8b42f..80aaad5 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -39,6 +39,12 @@ end end chip soc/intel/alderlake + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, -- To view, visit https://review.coreboot.org/c/coreboot/+/61264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I881ded944530b21d1c5e306089d32387c9c258b8 Gerrit-Change-Number: 61264 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cyan: Fix variant GPIOs
by Felix Held (Code Review) 07 Feb '22

07 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61585 ) Change subject: mb/google/cyan: Fix variant GPIOs ...................................................................... mb/google/cyan: Fix variant GPIOs - set GPSE-77 (Maxim jack detect) to NC for variants using Realtek audio - set GPSW-37 to NC for all variants (not used for LPE audio) - set GPSW-95 (Realtek jack detect) to NC for variant using Maxim audio - set GPSE-77 as maskable on variant using Maxim audio, to match mask setting for jack detect GPIO on other variants - set GPSE-81 as maskable on CELES to prevent interrupt storm (likely due to change in cherryview pinctrl driver circa kernel v3.18 which no longer masks all interrupts at init) Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61585 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: CoolStar Organization <coolstarorganization(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/cyan/variants/banon/gpio.c M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c 11 files changed, 20 insertions(+), 37 deletions(-) Approvals: build bot (Jenkins): Verified CoolStar Organization: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index b2d1cbe..4e91db4 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index b385ad7..71e209e 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -51,12 +51,11 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, + GPI(trig_edge_both, L1, P_20K_H, maskable, en_edge_detect, NA, NA), /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr assumed gpio number */ @@ -92,8 +91,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 9491c25..5723acf 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -51,8 +51,8 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPI(trig_edge_both, L0, NA, 0, en_edge_detect, NA, NA), + /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +90,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ GPIO_NC, /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ @@ -124,8 +123,7 @@ assert it low. */ GPIO_OUT_LOW, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + GPIO_NC, /* 95 RTK_AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ GPIO_END diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index c1b43b8..d285c04 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 4e4b01a..23fe4e1 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index ece6c80..13cc639 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 5a0c13a..2d308f5 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index cdf57a4..c57d28c 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 11071eb..d2e79f1 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index cef45aa..ede6229 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index 6e99330..3bb3931 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Gerrit-Change-Number: 61585 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: CoolStar Organization <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2022