coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede/var/magolor: Add custom Wifi SAR for magneto
by Shou-Chieh Hsu (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Henry Sun, Tyler Wang, Paul Fagerburg, Karthik Ramasubramanian, Felix Held. Shou-Chieh Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61438 ) Change subject: mb/google/dedede/var/magolor: Add custom Wifi SAR for magneto ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77f141372ba8e7b8f5849b00e115ad8bb1e7ca00 Gerrit-Change-Number: 61438 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Feb 2022 09:13:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add FSP header file for Alder Lake N FSP v2503_00
by Ronak Kanabar (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Varshit B Pandya, Saurabh Mishra, Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Usha P, Patrick Rudolph. Hello Varshit B Pandya, build bot (Jenkins), Saurabh Mishra, Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Usha P, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61547 to look at the new patch set (#3). Change subject: vendorcode/intel/fsp: Add FSP header file for Alder Lake N FSP v2503_00 ...................................................................... vendorcode/intel/fsp: Add FSP header file for Alder Lake N FSP v2503_00 The headers added are generated as per Alder Lake N FSP v2503_00. Changes include: - Add all header files for Alder Lake N FSP. - List of header files: FirmwareVersionInfoHob.h, FspmUpd.h, FspsUpd.h, FspUpd.h, MemInfoHob.h - Select FSP_HEADER_PATH BUG=b:213828776 BRANCH=None Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h 6 files changed, 7,581 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/61547/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b Gerrit-Change-Number: 61547 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform global reset lock
by Subrata Banik (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform global reset lock ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/9b68d97d_9a9ce51e PS8, Line 1022: if (cse_is_hfs1_spi_protected()) > >Any pointer to about who shares this recommendation and in what form ? I mean any document as such. > > You may refer the CSE Lite User Guide (or cse/cse_lite.c) to understand the CSE Lite update flow. The flow gives details what is the method coreboot use to update the CSE Lite firmware. From this, we can infer locking global reset always doesn't make any issue. > > >Note, `if clause` is about locking the CF9Lock and `else` is about keep the CF9 unlock to allow global reset. What you have asked originally at starting of this thread as below is against what you just said here. > > You have asked to skip locking the CF9Lock in case SoC user selects CSE LITE SKU. > > if (cse_cse_is_hfs1_spi_protected() && !CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU) > > And, in above comment you said, the recommendation is global reset remain locked for CSE lite? then why to leave the CF9Lock unlock for CSE Lite SKU? > > OMG, my code interpretation is wrong here. > > nit: > if (cse_cse_is_hfs1_spi_protected() || CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU)) @Sridhar, your original comment (!CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU)) and intension (lock global reset for CSE lite forcefully without bothering about HFWSTS[4]) is exactly opposite. You just missed `!` and created whole discussion roaming around that. If you would have been thoughtful while commenting then we could avoid such extra comment exchange cycle. `if (cse_cse_is_hfs1_spi_protected() || CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU))` is still okay to me with note that BIOS should lock down CF9GR bit even during manufacturing and re-manufacturing environment if HFSTS1 [4] is set with CSE Lite enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 09:05:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform global reset lock
by Sridhar Siricilla (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph, EricR Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform global reset lock ...................................................................... Patch Set 9: Code-Review+1 (2 comments) Patchset: PS9: Looks Good To Me. File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/ff4c4f74_553d2a43 PS8, Line 1022: if (cse_is_hfs1_spi_protected()) > > >Also, isn't that you said, CSE update doesn't bother about global reset using PMC rather use MEI […] >Any pointer to about who shares this recommendation and in what form ? I mean any document as such. You may refer the CSE Lite User Guide (or cse/cse_lite.c) to understand the CSE Lite update flow. The flow gives details what is the method coreboot use to update the CSE Lite firmware. From this, we can infer locking global reset always doesn't make any issue. >Note, `if clause` is about locking the CF9Lock and `else` is about keep the CF9 unlock to allow global reset. What you have asked originally at starting of this thread as below is against what you just said here. You have asked to skip locking the CF9Lock in case SoC user selects CSE LITE SKU. if (cse_cse_is_hfs1_spi_protected() && !CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU) And, in above comment you said, the recommendation is global reset remain locked for CSE lite? then why to leave the CF9Lock unlock for CSE Lite SKU? OMG, my code interpretation is wrong here. nit: if (cse_cse_is_hfs1_spi_protected() || CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU)) -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Feb 2022 08:56:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/drobit: Add fw_config probe for ALC5682-VD & VS
by Frank Chu (Code Review) 07 Feb '22

07 Feb '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61675 ) Change subject: mb/google/volteer/var/drobit: Add fw_config probe for ALC5682-VD & VS ...................................................................... mb/google/volteer/var/drobit: Add fw_config probe for ALC5682-VD & VS ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:204517112 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I5c1c9819af1e0bc2278dadeffb6b19c3f9068f30 --- M src/mainboard/google/volteer/variants/drobit/Makefile.inc M src/mainboard/google/volteer/variants/drobit/overridetree.cb A src/mainboard/google/volteer/variants/drobit/variant.c 3 files changed, 33 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/61675/1 diff --git a/src/mainboard/google/volteer/variants/drobit/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/Makefile.inc index 3454eec..4919fcd 100644 --- a/src/mainboard/google/volteer/variants/drobit/Makefile.inc +++ b/src/mainboard/google/volteer/variants/drobit/Makefile.inc @@ -6,3 +6,5 @@ ramstage-y += gpio.c ramstage-y += ramstage.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index a31017e..08b95f8 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" @@ -124,7 +131,7 @@ device ref i2c0 on chip drivers/i2c/generic - register "hid" = ""10EC5682"" + # register "hid" is set in variant.c because of FW_CONFIG register "name" = ""RT58"" register "desc" = ""Headset Codec"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" @@ -133,7 +140,7 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a alias audio_codec on end end chip drivers/i2c/max98373 register "vmon_slot_no" = "0" diff --git a/src/mainboard/google/volteer/variants/drobit/variant.c b/src/mainboard/google/volteer/variants/drobit/variant.c new file mode 100644 index 0000000..3effcdf --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <fw_config.h> +#include <drivers/i2c/hid/chip.h> +#include <device/device.h> + +static void audio_codec_update(void) +{ + struct device *codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config; + + config = codec->chip_info; + if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682))) + config->hid = "10EC5682"; + else + config->hid = "RTL5682"; +} +void variant_devtree_update(void) +{ + audio_codec_update(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c1c9819af1e0bc2278dadeffb6b19c3f9068f30 Gerrit-Change-Number: 61675 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/copano: Add fw_config probe for ALC5682-VD & VS
by Frank Chu (Code Review) 07 Feb '22

07 Feb '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61674 ) Change subject: mb/google/volteer/var/copano: Add fw_config probe for ALC5682-VD & VS ...................................................................... mb/google/volteer/var/copano: Add fw_config probe for ALC5682-VD & VS ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:218245715 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I081dcf5451c82c03592f954ee25267b31ad81753 --- M src/mainboard/google/volteer/variants/copano/Makefile.inc M src/mainboard/google/volteer/variants/copano/overridetree.cb A src/mainboard/google/volteer/variants/copano/variant.c 3 files changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/61674/1 diff --git a/src/mainboard/google/volteer/variants/copano/Makefile.inc b/src/mainboard/google/volteer/variants/copano/Makefile.inc index 343c7db..2af91aa 100644 --- a/src/mainboard/google/volteer/variants/copano/Makefile.inc +++ b/src/mainboard/google/volteer/variants/copano/Makefile.inc @@ -5,3 +5,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index 7ffa7ab..150db08 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end chip soc/intel/tigerlake # BitMask where bits [3:0] are Controller 0 Channel [3:0] and # bits [7:4] are Controller 1 Channel [3:0]. @@ -117,7 +124,7 @@ device ref i2c0 on chip drivers/i2c/generic - register "hid" = ""10EC5682"" + # register "hid" is set in variant.c because of FW_CONFIG register "name" = ""RT58"" register "desc" = ""Headset Codec"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" @@ -126,8 +133,7 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on - end + device i2c 1a alias audio_codec on end end chip drivers/i2c/max98373 register "vmon_slot_no" = "0" diff --git a/src/mainboard/google/volteer/variants/copano/variant.c b/src/mainboard/google/volteer/variants/copano/variant.c new file mode 100644 index 0000000..3effcdf --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <fw_config.h> +#include <drivers/i2c/hid/chip.h> +#include <device/device.h> + +static void audio_codec_update(void) +{ + struct device *codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config; + + config = codec->chip_info; + if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682))) + config->hid = "10EC5682"; + else + config->hid = "RTL5682"; +} +void variant_devtree_update(void) +{ + audio_codec_update(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I081dcf5451c82c03592f954ee25267b31ad81753 Gerrit-Change-Number: 61674 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/var/kano: Add gpios to lock
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak. EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61673 ) Change subject: mb/google/var/kano: Add gpios to lock ...................................................................... mb/google/var/kano: Add gpios to lock Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that kano boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I1d8c003b19381e6a76aff8c844546694c5710e53 --- M src/mainboard/google/brya/variants/kano/gpio.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/61673/1 diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 57975f7..8ef3c39 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -27,7 +27,7 @@ PAD_NC(GPP_A22, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */ @@ -37,11 +37,11 @@ /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC(GPP_D8, NONE), /* D16 : ISH_UART0_CTS# ==> PEN_PWR_EN */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG), /* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */ - PAD_CFG_GPI_SCI(GPP_D17, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> NC */ - PAD_NC(GPP_D18, NONE), + PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -50,9 +50,9 @@ /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E17 : THC0_SPI1_INT# ==> NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ @@ -72,9 +72,9 @@ /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H12 : I2C7_SDA ==> NC */ - PAD_NC(GPP_H12, NONE), + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> NC */ - PAD_NC(GPP_H13, NONE), + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), /* H19 : SRCCLKREQ4# ==> NC */ PAD_NC(GPP_H19, NONE), /* H20 : IMGCLKOUT1 ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d8c003b19381e6a76aff8c844546694c5710e53 Gerrit-Change-Number: 61673 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support
by EricR Lai (Code Review) 07 Feb '22

07 Feb '22

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61672 ) Change subject: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support ...................................................................... soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOCK support Add PAD_CFG_GPI_SCI_LOCK macro to support mainboard to lock GPI_SCI pins as applicable. BUG=b:216583542 TEST=build passed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I6bc435b38cd892c76fdb6107a5f1be9409e9207b --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/61672/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index a0a4eeb..ff47ddf 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -435,6 +435,14 @@ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) +/* General purpose input with lock, routed to SCI */ +#define PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, inv, lock_action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(lock_action)) + /* General purpose input, routed to SCI */ #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/61672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bc435b38cd892c76fdb6107a5f1be9409e9207b Gerrit-Change-Number: 61672 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS
by Frank Chu (Code Review) 07 Feb '22

07 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61671 ) Change subject: mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf5b3661e74a189390d25381e03448c28a966f38 Gerrit-Change-Number: 61671 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Feb 2022 08:37:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS
by Frank Chu (Code Review) 07 Feb '22

07 Feb '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61671 ) Change subject: mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS ...................................................................... mb/google/volteer/var/delbin: update fw_config probe for ALC5682-VD & VS use DEV_PTR to get codec HID for simplify the variant.c code ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:204523176 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Idf5b3661e74a189390d25381e03448c28a966f38 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/delbin/variant.c 2 files changed, 5 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/61671/1 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 3ff6bb2..76de7c6 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -145,7 +145,7 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a alias audio_codec on end end chip drivers/i2c/max98373 register "vmon_slot_no" = "0" diff --git a/src/mainboard/google/volteer/variants/delbin/variant.c b/src/mainboard/google/volteer/variants/delbin/variant.c index f502a1a..3effcdf 100644 --- a/src/mainboard/google/volteer/variants/delbin/variant.c +++ b/src/mainboard/google/volteer/variants/delbin/variant.c @@ -2,30 +2,18 @@ #include <baseboard/variants.h> #include <fw_config.h> -#include <drivers/i2c/generic/chip.h> -#include <soc/pci_devs.h> +#include <drivers/i2c/hid/chip.h> +#include <device/device.h> -extern struct chip_operations drivers_i2c_generic_ops; static void audio_codec_update(void) { - const struct device_path codec_path[] = { - {.type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_I2C0}, - {.type = DEVICE_PATH_I2C, .i2c.device = 0x1a} - }; - const struct device *codec = - find_dev_nested_path(pci_root_bus(), codec_path, - ARRAY_SIZE(codec_path)); + struct device *codec = DEV_PTR(audio_codec); struct drivers_i2c_generic_config *config; - if (!codec || (codec->chip_ops != &drivers_i2c_generic_ops) || - !codec->chip_info) - return; config = codec->chip_info; - if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682))) config->hid = "10EC5682"; - else if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, - AUDIO_CODEC_ALC5682I_VS))) + else config->hid = "RTL5682"; } void variant_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/61671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf5b3661e74a189390d25381e03448c28a966f38 Gerrit-Change-Number: 61671 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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