coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

1 participants
6828 discussions

[M] Change in coreboot[master]: soc/mediatek/mt8188: Add MIPI panel support for firmware display
by Yidi Lin (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70181 ) Change subject: soc/mediatek/mt8188: Add MIPI panel support for firmware display ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Gerrit-Change-Number: 70181 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:56:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8188: Add DSI support
by Rex-BC Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70184 ) Change subject: soc/mediatek/mt8188: Add DSI support ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/70184/comment/b03fafb9_9099d491 PS1, Line 9: setting settings https://review.coreboot.org/c/coreboot/+/70184/comment/aa25950d_cd5c2abd PS1, Line 9: For MT8188, we We https://review.coreboot.org/c/coreboot/+/70184/comment/c0acd824_2533d037 PS1, Line 13: emerge-geralt coreboot build pass emerge-geralt coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/70184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Gerrit-Change-Number: 70184 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:55:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: util/xcompile: Remove the extra "/" added after {XGCCPATH}
by Elyes Haouas (Code Review) 01 Dec '22

01 Dec '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70199 ) Change subject: util/xcompile: Remove the extra "/" added after {XGCCPATH} ...................................................................... util/xcompile: Remove the extra "/" added after {XGCCPATH} XGCCPATH is equal "util/crossgcc/xgcc/bin/", so remove the extra "/" added after "${XGCCPATH}. Change-Id: Ide312b101af7f6e3c9b69e45db24c7d5abb8fc24 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/xcompile/xcompile 1 file changed, 19 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/70199/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 7fba665..d275015 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -52,14 +52,14 @@ } -if [ "$("${XGCCPATH}/iasl" 2>/dev/null | grep -c ACPI)" -gt 0 ]; then - IASL=${XGCCPATH}/iasl +if [ "$("${XGCCPATH}iasl" 2>/dev/null | grep -c ACPI)" -gt 0 ]; then + IASL=${XGCCPATH}iasl elif [ "$(iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then IASL=iasl fi -if program_exists "${XGCCPATH}/gcc"; then - HOSTCC="${XGCCPATH}/gcc" +if program_exists "${XGCCPATH}gcc"; then + HOSTCC="${XGCCPATH}gcc" elif program_exists gcc; then HOSTCC=gcc elif program_exists cc; then @@ -72,8 +72,8 @@ # none, just set the compiler to false(1) which will break early enough if # used while being less confusing than errors about "g not found" when # "$HOSTCXX -g" evaluates to "-g" and make drops the leading dash. -if program_exists "${XGCCPATH}/g++"; then - HOSTCXX="${XGCCPATH}/g++" +if program_exists "${XGCCPATH}g++"; then + HOSTCXX="${XGCCPATH}g++" elif program_exists g++; then HOSTCXX=g++ elif program_exists c++; then -- To view, visit https://review.coreboot.org/c/coreboot/+/70199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide312b101af7f6e3c9b69e45db24c7d5abb8fc24 Gerrit-Change-Number: 70199 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8188: Add MIPI panel support for firmware display
by Rex-BC Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70181 ) Change subject: soc/mediatek/mt8188: Add MIPI panel support for firmware display ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70181/comment/e74d1b81_78d1b7e5 PS1, Line 9: For geralt project, we also support MIPI panel as our firmware : display. So add this patch to configure ddp to choose eDP display or : MIPI panel display. fit 72 per line -- To view, visit https://review.coreboot.org/c/coreboot/+/70181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Gerrit-Change-Number: 70181 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:53:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`
by Reka Norman (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kangheui Won, Haribalaraman Ramasubramanian, Rizwan Qureshi, Meera Ravindranath, Nick Vaccaro, Eric Lai, Divagar Mohandass. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70180 ) Change subject: soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE` ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Verified that nirwen UFS SKU still goes to S0i3. Could someone at Intel please verify that this doesn't reintroduce the original PLT issue CB:68251 was meant to fix? -- To view, visit https://review.coreboot.org/c/coreboot/+/70180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317 Gerrit-Change-Number: 70180 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/mediatek: Fix DSI register definition for MT8186
by Rex-BC Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Liju-Clr Chen, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70183 ) Change subject: soc/mediatek: Fix DSI register definition for MT8186 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70183/comment/9bc06f39_018a616f PS1, Line 10: version versions -- To view, visit https://review.coreboot.org/c/coreboot/+/70183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Gerrit-Change-Number: 70183 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:52:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8188: Add MIPI panel support for firmware display
by Rex-BC Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70181 ) Change subject: soc/mediatek/mt8188: Add MIPI panel support for firmware display ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Gerrit-Change-Number: 70181 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:51:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8188: Add DSI support
by Liju-Clr Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Rex-BC Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70184 to review the following change. Change subject: soc/mediatek/mt8188: Add DSI support ...................................................................... soc/mediatek/mt8188: Add DSI support For MT8188, we need to add DSI and MIPI_TX setting to support MIPI panel. BUG=b:244208960 TEST=emerge-geralt coreboot build pass Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/include/soc/addressmap.h A src/soc/mediatek/mt8188/include/soc/dsi.h 3 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/70184/1 diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 59ec553..7ac988b 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c +ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index da95952..a5a3c00 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -77,6 +77,7 @@ I2C3_BASE = IO_PHYS + 0x01282000, SFLASH_REG_BASE = IO_PHYS + 0x0132C000, IOCFG_RM_BASE = IO_PHYS + 0x01C00000, + MIPITX_BASE = IO_PHYS + 0x01C80000, I2C1_BASE = IO_PHYS + 0x01E00000, I2C4_BASE = IO_PHYS + 0x01E01000, IOCFG_LT_BASE = IO_PHYS + 0x01E10000, @@ -95,6 +96,7 @@ DISP_AAL0_BASE = IO_PHYS + 0x0C005000, DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000, DISP_DITHER0_BASE = IO_PHYS + 0x0C007000, + DSI0_BASE = IO_PHYS + 0x0C008000, DISP_OVL1_BASE = IO_PHYS + 0x0C00A000, DP_INTF0_BASE = IO_PHYS + 0x0C015000, DISP_MUTEX_BASE = IO_PHYS + 0x0C016000, diff --git a/src/soc/mediatek/mt8188/include/soc/dsi.h b/src/soc/mediatek/mt8188/include/soc/dsi.h new file mode 100644 index 0000000..1a4eab4 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dsi.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8188_DSI_H +#define SOC_MEDIATEK_MT8188_DSI_H + +#include <soc/dsi_common.h> +#include <soc/dsi_register_v2.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Gerrit-Change-Number: 70184 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/mediatek: Fix DSI register definition for MT8186
by Liju-Clr Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Rex-BC Chen. Hello Rex-BC Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70183 to review the following change. Change subject: soc/mediatek: Fix DSI register definition for MT8186 ...................................................................... soc/mediatek: Fix DSI register definition for MT8186 The DSI CMDQ offset for MT8186 is different from previous SoCs. Therefore, we define two version for DSI register header files. The v1 is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188. BUG=b:244208960 TEST=build pass BRANCH=corsola Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/dsi_common.h A src/soc/mediatek/common/include/soc/dsi_register_v1.h A src/soc/mediatek/common/include/soc/dsi_register_v2.h M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/include/soc/dsi.h M src/soc/mediatek/mt8186/include/soc/dsi.h M src/soc/mediatek/mt8192/include/soc/dsi.h 7 files changed, 134 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/70183/1 diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index bc4bfa1..a0acce8 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -45,53 +45,8 @@ MIPI_DSI_MODE_LINE_END = BIT(12), }; -struct dsi_regs { - u32 dsi_start; - u8 reserved0[4]; - u32 dsi_inten; - u32 dsi_intsta; - u32 dsi_con_ctrl; - u32 dsi_mode_ctrl; - u32 dsi_txrx_ctrl; - u32 dsi_psctrl; - u32 dsi_vsa_nl; - u32 dsi_vbp_nl; - u32 dsi_vfp_nl; - u32 dsi_vact_nl; - u32 dsi_lfr_con; /* Available since MT8183 */ - u32 dsi_lfr_sta; /* Available since MT8183 */ - u32 dsi_size_con; /* Available since MT8183 */ - u32 dsi_vfp_early_stop; /* Available since MT8183 */ - u32 reserved1[4]; - u32 dsi_hsa_wc; - u32 dsi_hbp_wc; - u32 dsi_hfp_wc; - u32 dsi_bllp_wc; - u32 dsi_cmdq_size; - u32 dsi_hstx_cklp_wc; - u8 reserved2[156]; - u32 dsi_phy_lccon; - u32 dsi_phy_ld0con; - u8 reserved3[4]; - u32 dsi_phy_timecon0; - u32 dsi_phy_timecon1; - u32 dsi_phy_timecon2; - u32 dsi_phy_timecon3; - u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[92]; - u32 dsi_force_commit; /* Available since MT8183 */ - u8 reserved6[108]; - u32 dsi_cmdq[128]; -}; static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -check_member(dsi_regs, dsi_phy_lccon, 0x104); -check_member(dsi_regs, dsi_phy_timecon3, 0x11c); -check_member(dsi_regs, dsi_vm_cmd_con, 0x130); -check_member(dsi_regs, dsi_force_commit, 0x190); -check_member(dsi_regs, dsi_cmdq, 0x200); - /* DSI_INTSTA */ enum { LPRX_RD_RDY_INT_FLAG = BIT(0), diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v1.h b/src/soc/mediatek/common/include/soc/dsi_register_v1.h new file mode 100644 index 0000000..ec5dfda --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dsi_register_v1.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DSI_REGISTER_V1_H +#define DSI_REGISTER_V1_H + +#include <commonlib/helpers.h> +#include <soc/addressmap.h> +#include <types.h> + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; /* Available since MT8183 */ + u32 dsi_lfr_sta; /* Available since MT8183 */ + u32 dsi_size_con; /* Available since MT8183 */ + u32 dsi_vfp_early_stop; /* Available since MT8183 */ + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; /* Available since MT8183 */ + u8 reserved6[108]; + u32 dsi_cmdq[128]; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq, 0x200); + +#endif /* DSI_REGISTER_V1_H */ diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v2.h b/src/soc/mediatek/common/include/soc/dsi_register_v2.h new file mode 100644 index 0000000..17809c7 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dsi_register_v2.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DSI_REGISTER_V2_H +#define DSI_REGISTER_V2_H + +#include <commonlib/helpers.h> +#include <soc/addressmap.h> +#include <types.h> + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; /* Available since MT8183 */ + u32 dsi_lfr_sta; /* Available since MT8183 */ + u32 dsi_size_con; /* Available since MT8183 */ + u32 dsi_vfp_early_stop; /* Available since MT8183 */ + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; /* Available since MT8183 */ + u8 reserved6[2924]; + u32 dsi_cmdq[128]; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq, 0xd00); + +#endif /* DSI_REGISTER_V2_H */ diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 6f9b301..22010c9 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -4,6 +4,7 @@ #define _DSI_REG_H_ #include <soc/dsi_common.h> +#include <soc/dsi_register_v1.h> #include <types.h> /* DSI features */ diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 9da79e6..3fcc281 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_DSI_H #include <soc/dsi_common.h> +#include <soc/dsi_register_v1.h> #include <types.h> /* DSI features */ diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h index 2cb9159..1a7c2f99 100644 --- a/src/soc/mediatek/mt8186/include/soc/dsi.h +++ b/src/soc/mediatek/mt8186/include/soc/dsi.h @@ -9,6 +9,7 @@ #define SOC_MEDIATEK_MT8186_DSI_H #include <soc/dsi_common.h> +#include <soc/dsi_register_v2.h> /* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 100 diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h index ed3d0d8..9ce55fa 100644 --- a/src/soc/mediatek/mt8192/include/soc/dsi.h +++ b/src/soc/mediatek/mt8192/include/soc/dsi.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_DSI_H #include <soc/dsi_common.h> +#include <soc/dsi_register_v1.h> /* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 100 -- To view, visit https://review.coreboot.org/c/coreboot/+/70183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Gerrit-Change-Number: 70183 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by build bot (Jenkins) (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Tim Van Patten, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 74: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164966): https://review.coreboot.org/c/coreboot/+/68471/comment/0826caf7_ef4ea7bf PS74, Line 14: mode. Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/soc/amd/common/acpi/dptc.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164966): https://review.coreboot.org/c/coreboot/+/68471/comment/b19cb461_f47eaf50 PS74, Line 34: #if CONFIG(FEATURE_DYNAMIC_DPTC) trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 74 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:47:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2022