Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70180 )
Change subject: soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`
......................................................................
soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`
This patch ensures dropping of the duplicate macro introduced with
'commit 9e4488ab06fd9c4 ("soc/intel/{adl,cmn}: Add/Remove LTR
disqualification for UFS")'
`PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range
which can be used as is even in ufs.asl file.
BUG=b:252975357
TEST=Build and boot nirwen and see no issues in PLT runs.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317
---
M src/soc/intel/alderlake/include/soc/ufs.h
1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/70180/1
diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h
index e3a98f2..a7efc8a 100644
--- a/src/soc/intel/alderlake/include/soc/ufs.h
+++ b/src/soc/intel/alderlake/include/soc/ufs.h
@@ -24,5 +24,4 @@
#define R_SCS_PCR_1078 0x1078
#define R_PMC_PWRM_LTR_IGN 0x1b0c
-#define PCH_PWRM_BASE_SIZE 0x1e30
#endif
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
......................................................................
mb/google/nissa/var/xivu: Fine-tune eMMC DLL
Fine-tune eMMC DLL based on Xivu EVT system.
BUG=b:256538132
TEST= executed 3000 cycles of cold boot successfully
Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be
Signed-off-by: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xivu/overridetree.cb
1 file changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69892/8
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Lawrence Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69892 )
Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69892/comment/6f688bb4_7b64538e
PS2, Line 12: TEST="Use the value to boot on Xivu successfully."
> We still need the `TEST=` field, just remove the quote symbol. […]
Added "TEST" field.
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Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
......................................................................
mb/google/nissa/var/xivu: Fine-tune eMMC DLL
Fine-tune eMMC DLL based on Xivu EVT system.
BUG=b:256538132
TEST= "executed 3000 cycles of cold boot successfully"
Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be
Signed-off-by: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xivu/overridetree.cb
1 file changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69892/7
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Change subject: mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Please add a follow up to remove the another parameter when you have time to test it.
OK
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Change subject: mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad
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Patch Set 3:
(1 comment)
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PS3:
Please add a follow up to remove the another parameter when you have time to test it.
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Change subject: mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad
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Patch Set 3: Code-Review+2
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Change subject: mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/anahera/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/70171/comment/8481740c_be2baa47
PS3, Line 69: .speed_config[0] = {
> I think you only need one of the parameter. try remove rise_time_ns and fall_time_ns.
Hi Eric,
It's urgent case. We already use the setting and build coreboot. Elan help to measure and confirm all timing meets their SPEC.
If we try to remove rise_time_ns/fall_time_ns, it could take time to measure again.
If it's not must modification, hope you can understand
Thanks
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