coreboot-gerrit December 2022

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Add MIPI panel support for firmware display
by Liju-Clr Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Rex-BC Chen. Hello Rex-BC Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70181 to review the following change. Change subject: soc/mediatek/mt8188: Add MIPI panel support for firmware display ...................................................................... soc/mediatek/mt8188: Add MIPI panel support for firmware display For geralt project, we also support MIPI panel as our firmware display. So add this patch to configure ddp to choose eDP display or MIPI panel display. BUG=b:244208960 TEST=test firmware display pass for both eDP and MIPI panel on MT8188 EVB. Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> --- M src/mainboard/google/geralt/display.c M src/soc/mediatek/mt8188/ddp.c M src/soc/mediatek/mt8188/include/soc/ddp.h 3 files changed, 55 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/70181/1 diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c index 3db9171..eaee6c8 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/mainboard/google/geralt/display.c @@ -55,7 +55,7 @@ edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - mtk_ddp_mode_set(&edid); + mtk_ddp_mode_set(&edid, DISP_PATH_EDP); info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); if (info) fb_set_orientation(info, LB_FB_ORIENTATION_NORMAL); diff --git a/src/soc/mediatek/mt8188/ddp.c b/src/soc/mediatek/mt8188/ddp.c index 8d2d43a..ce14fa7 100644 --- a/src/soc/mediatek/mt8188/ddp.c +++ b/src/soc/mediatek/mt8188/ddp.c @@ -6,24 +6,36 @@ #include <soc/addressmap.h> #include <soc/ddp.h> -static void disp_config_main_path_connection(void) +static void disp_config_main_path_connection(enum disp_path_sel path) { /* ovl0 */ write32(&mmsys_cfg->mmsys_ovl_mout_en, DISP_OVL0_TO_DISP_RDMA0); - write32(&mmsys_cfg->mmsys_dp_intf0_sel_in, - SEL_IN_DP_INTF0_FROM_DISP_DITHER0); - write32(&mmsys_cfg->mmsys_dither0_sel_out, - SEL_OUT_DISP_DITHER0_TO_DP_INTF0); + + if (path == DISP_PATH_EDP) { + write32(&mmsys_cfg->mmsys_dp_intf0_sel_in, + SEL_IN_DP_INTF0_FROM_DISP_DITHER0); + write32(&mmsys_cfg->mmsys_dither0_sel_out, + SEL_OUT_DISP_DITHER0_TO_DP_INTF0); + } else { + write32(&mmsys_cfg->mmsys_dsi0_sel_in, + SEL_IN_DSI0_FROM_DISP_DITHER0); + write32(&mmsys_cfg->mmsys_dither0_sel_out, + SEL_OUT_DISP_DITHER0_TO_DSI0); + } } -static void disp_config_main_path_mutex(void) +static void disp_config_main_path_mutex(enum disp_path_sel path) { write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); - /* Clock source from DP_INTF0 */ - write32(&disp_mutex->mutex[0].ctl, - MUTEX_SOF_DP_INTF0 | (MUTEX_SOF_DP_INTF0 << 7)); + if (path == DISP_PATH_EDP) + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DP_INTF0 | (MUTEX_SOF_DP_INTF0 << 7)); + else + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 7)); + write32(&disp_mutex->mutex[0].en, BIT(0)); } @@ -94,7 +106,7 @@ write32(&regs->en, PQ_EN); } -static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh, enum disp_path_sel path) { u32 idx; const u32 pixel_clk = width * height * vrefresh; @@ -114,8 +126,8 @@ gamma_config(width, height); postmask_config(width, height); dither_config(width, height); - disp_config_main_path_connection(); - disp_config_main_path_mutex(); + disp_config_main_path_connection(path); + disp_config_main_path_mutex(path); } static void disp_clock_on(void) @@ -133,7 +145,7 @@ write32p(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0, 0); } -void mtk_ddp_mode_set(const struct edid *edid) +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; @@ -156,7 +168,7 @@ __func__, vrefresh); } - main_disp_path_setup(width, height, vrefresh); + main_disp_path_setup(width, height, vrefresh, path); rdma_start(); ovl_layer_config(fmt, bpp, width, height); } diff --git a/src/soc/mediatek/mt8188/include/soc/ddp.h b/src/soc/mediatek/mt8188/include/soc/ddp.h index 26f0151..475485e 100644 --- a/src/soc/mediatek/mt8188/include/soc/ddp.h +++ b/src/soc/mediatek/mt8188/include/soc/ddp.h @@ -82,7 +82,8 @@ CG_CON0_DISP_AAL0 | CG_CON0_DISP_GAMMA0 | CG_CON0_DISP_DITHER0 | - CG_CON0_DISP_DP_INTF0, + CG_CON0_DISP_DP_INTF0 | + CG_CON0_DISP_DSI0, CG_CON0_ALL = 0xffffffff }; @@ -122,7 +123,8 @@ CG_CON2_DPI_DPI0 = BIT(8), CG_CON2_DP_INTF0 = BIT(16), - CG_CON2_DISP_ALL = CG_CON2_DP_INTF0, + CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 | + CG_CON2_DP_INTF0, CG_CON2_ALL = 0xffffffff }; @@ -280,7 +282,12 @@ SMI_LARB_PORT_L0_OVL_RDMA0 = 0xF88, }; +enum disp_path_sel { + DISP_PATH_EDP = 0, + DISP_PATH_MIPI, +}; + void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Gerrit-Change-Number: 70181 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6
by Elyes Haouas (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth, Paul Menzel, Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69700/comment/3e4e6c1d_4581f48f PS7, Line 8: > Please add the comment back. Done Patchset: PS11: Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:22:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6
by Elyes Haouas (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth, Arthur Heymans, Elyes Haouas. Hello Felix Singer, build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69700 to look at the new patch set (#11). Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 ...................................................................... crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 Tested with BUILD_TIMELESS=1: binaries stay the same for qemu-i440fx. Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum 11 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/69700/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Dinesh Gehlot (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70172 to look at the new patch set (#5). Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of commit 7c6dd796f26f (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/70172/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 5 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Update cpu and pch tracehub modes
by Sridhar Siricilla (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Subrata Banik, Maulik Vaghela, Paul Menzel. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64438 ) Change subject: soc/intel/alderlake: Update cpu and pch tracehub modes ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Need to understand what is the path forward with this patch trend ? Do you still want to block the Patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/64438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Gerrit-Change-Number: 64438 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 01 Dec 2022 04:37:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70180 ) Change subject: soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE` ...................................................................... soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE` This patch ensures dropping of the duplicate macro introduced with 'commit 9e4488ab06fd9c4 ("soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS")' `PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range which can be used as is even in ufs.asl file. BUG=b:252975357 TEST=Build and boot nirwen and see no issues in PLT runs. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317 --- M src/soc/intel/alderlake/include/soc/ufs.h 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/70180/1 diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h index e3a98f2..a7efc8a 100644 --- a/src/soc/intel/alderlake/include/soc/ufs.h +++ b/src/soc/intel/alderlake/include/soc/ufs.h @@ -24,5 +24,4 @@ #define R_SCS_PCR_1078 0x1078 #define R_PMC_PWRM_LTR_IGN 0x1b0c -#define PCH_PWRM_BASE_SIZE 0x1e30 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317 Gerrit-Change-Number: 70180 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
by Lawrence Chang (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Henry Sun, Paul Menzel, Reka Norman, Nick Vaccaro, Shou-Chieh Hsu. Hello build bot (Jenkins), Tarun Tuli, Jamie Chen, Henry Sun, Kangheui Won, Reka Norman, Nick Vaccaro, Shou-Chieh Hsu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69892 to look at the new patch set (#8). Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL ...................................................................... mb/google/nissa/var/xivu: Fine-tune eMMC DLL Fine-tune eMMC DLL based on Xivu EVT system. BUG=b:256538132 TEST= executed 3000 cycles of cold boot successfully Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Signed-off-by: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69892/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/69892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Gerrit-Change-Number: 69892 Gerrit-PatchSet: 8 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
by Lawrence Chang (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Henry Sun, Paul Menzel, Reka Norman, Nick Vaccaro, Shou-Chieh Hsu. Lawrence Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69892 ) Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69892/comment/6f688bb4_7b64538e PS2, Line 12: TEST="Use the value to boot on Xivu successfully." > We still need the `TEST=` field, just remove the quote symbol. […] Added "TEST" field. -- To view, visit https://review.coreboot.org/c/coreboot/+/69892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Gerrit-Change-Number: 69892 Gerrit-PatchSet: 7 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 03:23:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shou-Chieh Hsu <shouchieh(a)google.com> Comment-In-Reply-To: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
by Lawrence Chang (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Henry Sun, Paul Menzel, Reka Norman, Nick Vaccaro, Lawrence Chang. Hello build bot (Jenkins), Tarun Tuli, Jamie Chen, Henry Sun, Kangheui Won, Reka Norman, Nick Vaccaro, Shou-Chieh Hsu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69892 to look at the new patch set (#7). Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL ...................................................................... mb/google/nissa/var/xivu: Fine-tune eMMC DLL Fine-tune eMMC DLL based on Xivu EVT system. BUG=b:256538132 TEST= "executed 3000 cycles of cold boot successfully" Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Signed-off-by: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69892/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Gerrit-Change-Number: 69892 Gerrit-PatchSet: 7 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad
by Wisley Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Chen Wisley, Nick Vaccaro. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70171 ) Change subject: mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/anahera/overridetree.cb: https://review.coreboot.org/c/coreboot/+/70171/comment/d30f2f74_ad38a77c PS3, Line 69: .speed_config[0] = { > Hi Eric, […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/70171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9036a604a90558911c4f8a492db9f1f0f28bf404 Gerrit-Change-Number: 70171 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 03:18:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2022