coreboot-gerrit December 2022

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[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... soc/intel/meteorlake: Log CSE RO write protection info for MTL The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/meteorlake/me.c 1 file changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, but someone else must approve Sridhar Siricilla: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/me.c b/src/soc/intel/meteorlake/me.c index 4f2bc53..265fd36 100644 --- a/src/soc/intel/meteorlake/me.c +++ b/src/soc/intel/meteorlake/me.c @@ -160,6 +160,9 @@ hfsts5.fields.cpu_debug_disabled ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts5.fields.txt_support ? "YES" : "NO"); + + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_log_ro_write_protection_info(manufacturing_mode); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 15 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Sridhar Siricilla, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69978 ) Change subject: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/69978/comment/e3abb552_e6bbdc40 PS6, Line 241: send_cse_eop_with_late_finalize > > nit: It is better function prefixed with cse_*. > > I would prefer to keep the name starting with a `verb` instead of `cse` at starting. Refer to the line #174, #202. marking this resolve now, hoping there is no confusion with function name -- To view, visit https://review.coreboot.org/c/coreboot/+/69978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Gerrit-Change-Number: 69978 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 09:27:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Configure `SLP_S0_GATE_R` lowby default
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70196 ) Change subject: mb/google/rex: Configure `SLP_S0_GATE_R` lowby default ...................................................................... mb/google/rex: Configure `SLP_S0_GATE_R` lowby default This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SKL_S0_L` signal is `low` while the system is in S0ix. Having `SLP_S0_GATE_R` configured to `high` makes `SYS_SLP_S0IX_L` remain `high` always and repo the wrong system state to EC. BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce --- M src/mainboard/google/rex/variants/rex0/gpio.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/1 diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index ecda8bf..b76142a 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -316,7 +316,7 @@ /* GPP_H13 : [] ==> CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* GPP_H14 : [] ==> SLP_S0_GATE_R */ - PAD_CFG_GPO(GPP_H14, 1, PLTRST), + PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPP_H15 : net NC is not present in the given design */ PAD_NC(GPP_H15, NONE), /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/70196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Gerrit-Change-Number: 70196 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/xcompile: Remove the extra "/" added after {XGCCPATH}
by Jakub Czapiga (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth, Elyes Haouas. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70199 ) Change subject: util/xcompile: Remove the extra "/" added after {XGCCPATH} ...................................................................... Patch Set 1: (2 comments) File util/xcompile/xcompile: https://review.coreboot.org/c/coreboot/+/70199/comment/14dc9caf_28ca1967 PS1, Line 16: XGCCPATH=$1 What if someone has crossgcc compiled under different path (like ChromeOS SDK does it)? This change can potentially break many build scripts out there, so I'd be careful. https://review.coreboot.org/c/coreboot/+/70199/comment/460c49e6_6044f847 PS1, Line 21: XGCCPATH=${XGCCPATH:-"$(pwd)/../../../../util/crossgcc/xgcc/bin/"} I think it would be better to just remove slashes from these paths instead and leave them in other places for clarity and readability. (Even `dirname $DIR`) returns path without trailing slash) -- To view, visit https://review.coreboot.org/c/coreboot/+/70199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide312b101af7f6e3c9b69e45db24c7d5abb8fc24 Gerrit-Change-Number: 70199 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 01 Dec 2022 09:16:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 ...................................................................... crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 Tested with BUILD_TIMELESS=1: binaries stay the same for qemu-i440fx. Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69700 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum 11 files changed, 21 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5ade86b..5b26922 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -39,7 +39,7 @@ BINUTILS_VERSION=2.37 IASL_VERSION="R10_20_22" # CLANG version number -CLANG_VERSION=15.0.0 +CLANG_VERSION=15.0.6 CMAKE_VERSION=3.25.0 NASM_VERSION=2.15.05 diff --git a/util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum deleted file mode 100644 index b83f55c..0000000 --- a/util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7b47dbb51bd2de28174d8425f4fe9523880bc7b8 tarballs/clang-15.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..8a98168 --- /dev/null +++ b/util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +f8bf6effb93f45fc66cfc4e9e0e160b7845dd9d6 tarballs/clang-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum deleted file mode 100644 index 58fa9d8..0000000 --- a/util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -65c804e2539753ab350a0960b378ce66bc57b0e9 tarballs/clang-tools-extra-15.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..60d65a6 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +bd3df3ff940ea928f74c467691be0e68c5fc014e tarballs/clang-tools-extra-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum deleted file mode 100644 index 4bf97ee..0000000 --- a/util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -56ca883308b1b30cb981c86038eb677db9cc8eb5 tarballs/cmake-15.0.0.src.tar.xz diff --git a/util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..43c36a3 --- /dev/null +++ b/util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +507185c7c4ce9cd6f4926b05b869fe3e8c945041 tarballs/cmake-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum deleted file mode 100644 index add3a44..0000000 --- a/util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -15879f50459c7b2e7b5fb77c6b845c39c91a04fc tarballs/compiler-rt-15.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..53c1413 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +ff5f8cdcfc6fbc5c0a68a76da33c88fd3f272951 tarballs/compiler-rt-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum deleted file mode 100644 index 0e033aa..0000000 --- a/util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6f7f53d45ae8d207a6d72fd8ac380160f240d37e tarballs/llvm-15.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..d5cb9a6 --- /dev/null +++ b/util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +60e9a385dde9a10e6ef7009ce342a119d3432eef tarballs/llvm-15.0.6.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth, Paul Menzel, Arthur Heymans, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 01 Dec 2022 09:15:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade CMake from 3.24.2 to 3.25.0
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69715 ) Change subject: crossgcc: Upgrade CMake from 3.24.2 to 3.25.0 ...................................................................... crossgcc: Upgrade CMake from 3.24.2 to 3.25.0 Change-Id: Iebccaf984c2c8b449c8f152484a4df1e75e74fd8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69715 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.24.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum 3 files changed, 16 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6015102..5ade86b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -40,7 +40,7 @@ IASL_VERSION="R10_20_22" # CLANG version number CLANG_VERSION=15.0.0 -CMAKE_VERSION=3.24.2 +CMAKE_VERSION=3.25.0 NASM_VERSION=2.15.05 # GCC toolchain archive locations diff --git a/util/crossgcc/sum/cmake-3.24.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.24.2.tar.gz.cksum deleted file mode 100644 index 81ad811..0000000 --- a/util/crossgcc/sum/cmake-3.24.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -c2441ed6e00ba2c5ad0b7cd06afa8057769b9c1b tarballs/cmake-3.24.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum new file mode 100644 index 0000000..bb3d397 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum @@ -0,0 +1 @@ +c791c64877ee550b78613bf089f2a7a58d3b1b65 tarballs/cmake-3.25.0.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/69715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebccaf984c2c8b449c8f152484a4df1e75e74fd8 Gerrit-Change-Number: 69715 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: crossgcc: Upgrade CMake from 3.24.2 to 3.25.0
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69715 ) Change subject: crossgcc: Upgrade CMake from 3.24.2 to 3.25.0 ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebccaf984c2c8b449c8f152484a4df1e75e74fd8 Gerrit-Change-Number: 69715 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 01 Dec 2022 09:14:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Extend sd_hold for touchpad
by Chen Wisley (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70195 to review the following change. Change subject: mb/google/nissa/var/yaviks: Extend sd_hold for touchpad ...................................................................... mb/google/nissa/var/yaviks: Extend sd_hold for touchpad Extend sd_hold to meet touchpad SPEC BUG=None TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98 --- M src/mainboard/google/brya/variants/yaviks/overridetree.cb 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/70195/1 diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb index 6c58e4e..e70e57f 100644 --- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb @@ -72,7 +72,7 @@ .speed = I2C_SPEED_FAST, .scl_lcnt = 158, .scl_hcnt = 79, - .sda_hold = 7, + .sda_hold = 40, } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/70195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98 Gerrit-Change-Number: 70195 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/zydron: Set touchpads to use probed flag
by David Wu (Code Review) 01 Dec '22

01 Dec '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70194 ) Change subject: mb/google/brya/var/zydron: Set touchpads to use probed flag ...................................................................... mb/google/brya/var/zydron: Set touchpads to use probed flag This patch fix touchpads function can't work issue. BUG=b:258583945 TEST=build pass and check touchpads function work. Change-Id: Ib9a5ad5dc97cfaf1c10e7ff1e68b72af6add64c6 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/zydron/overridetree.cb 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/70194/1 diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb index f8a14be..1c78e8e 100644 --- a/src/mainboard/google/brya/variants/zydron/overridetree.cb +++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb @@ -383,7 +383,7 @@ register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" register "wake" = "GPE0_DW2_14" - register "detect" = "1" + register "probed" = "1" device i2c 15 on end end chip drivers/i2c/hid @@ -391,7 +391,7 @@ register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" register "generic.wake" = "GPE0_DW2_14" - register "generic.detect" = "1" + register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/70194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a5ad5dc97cfaf1c10e7ff1e68b72af6add64c6 Gerrit-Change-Number: 70194 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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