coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

1 participants
6828 discussions

[S] Change in coreboot[master]: nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69293 ) ( 16 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree ...................................................................... nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/northbridge/intel/gm45/northbridge.c 4 files changed, 22 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 57f1f37..0bfdbc9 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -9,6 +9,7 @@ register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_p device lapic 0 on end end @@ -28,6 +29,7 @@ register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops device pci 00.0 on subsystemid 0x17aa 0x20e0 end # host bridge diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 059dc00..dc059f0 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -9,6 +9,7 @@ register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end @@ -28,6 +29,7 @@ register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops device pci 00.0 on subsystemid 0x17aa 0x20e0 end # host bridge diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index c9c1896..d4b4aef 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -2,6 +2,7 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end @@ -21,6 +22,7 @@ register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops subsystemid 0x4352 0x8986 device pci 00.0 on end # host bridge device pci 02.0 on end # VGA diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index df5526c..31e3de4 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -200,7 +200,7 @@ set_above_4g_pci(dev); } -static struct device_operations pci_domain_ops = { +struct device_operations gm45_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, @@ -210,22 +210,12 @@ .acpi_name = northbridge_acpi_name, }; -static struct device_operations cpu_bus_ops = { +struct device_operations gm45_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - static void gm45_init(void *const chip_info) { int dev, fn, bit_base; @@ -265,6 +255,5 @@ struct chip_operations northbridge_intel_gm45_ops = { CHIP_NAME("Intel GM45 Northbridge") - .enable_dev = enable_dev, .init = gm45_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Gerrit-Change-Number: 69293 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: util/autoport: Update devicetree generation
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69501 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/autoport: Update devicetree generation ...................................................................... util/autoport: Update devicetree generation CPU nodes are now declared in a common chipset.cb. TESTED: generates a proper devicetree for x220 based on logs. Change-Id: Ic1f2d3d611aa3979b846706b6f743f79a3c4e54d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69501 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/autoport/sandybridge.go 1 file changed, 17 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 950286c..a60018e 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -36,34 +36,6 @@ }, Children: []DevTreeNode{ { - Chip: "cpu_cluster", - Dev: 0, - Children: []DevTreeNode{ - { - Chip: "cpu/intel/model_206ax", - Comment: "FIXME: check all registers", - Registers: map[string]string{ - /* FIXME:XX hardcoded. */ - "acpi_c1": "1", - "acpi_c2": "3", - "acpi_c3": "5", - }, - Children: []DevTreeNode{ - { - Chip: "lapic", - Dev: 0, - }, - { - Chip: "lapic", - Dev: 0xacac, - Disabled: true, - }, - }, - }, - }, - }, - - { Chip: "domain", Dev: 0, PCIController: true, -- To view, visit https://review.coreboot.org/c/coreboot/+/69501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1f2d3d611aa3979b846706b6f743f79a3c4e54d Gerrit-Change-Number: 69501 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: cpu/intel/model_206ax: Remove fake lapic device
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59316 ) Change subject: cpu/intel/model_206ax: Remove fake lapic device ...................................................................... cpu/intel/model_206ax: Remove fake lapic device Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic device is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/northbridge.c 12 files changed, 59 insertions(+), 90 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 06913bc..d2d6467 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -95,18 +95,9 @@ return msr.lo & 0xffff; } -static void generate_C_state_entries(void) +static void generate_C_state_entries(const struct device *dev) { - struct device *lapic; - struct cpu_intel_model_206ax_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; + struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info; const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; @@ -324,7 +315,7 @@ cpuID-1, cores_per_package); /* Generate C-state tables */ - generate_C_state_entries(); + generate_C_state_entries(device); /* Generate T-state tables */ generate_T_state_entries( diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index a46c7bf..13cf3163 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - /* Keep this in sync with acpi.c */ enum cpu_acpi_level { CPU_ACPI_DISABLED = 0, diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 8bb1091..6522e0fe 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -211,18 +211,11 @@ wrmsr(MSR_PP1_CURRENT_CONFIG, msr); } -static void configure_thermal_target(void) +static void configure_thermal_target(struct device *dev) { - struct cpu_intel_model_206ax_config *conf; - struct device *lapic; + struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info; msr_t msr; - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { @@ -346,7 +339,7 @@ configure_misc(); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_thermal_target(cpu); set_aesni_lock(); diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 8f94378..62b0b0b 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -1,10 +1,8 @@ chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "tcc_offset" = "5" # TCC of 95C - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/model_206ax + device cpu_cluster 0 on end + + register "tcc_offset" = "5" # TCC of 95C end device domain 0 on diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 77f58c2..87d0ed9 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -19,14 +19,10 @@ register "max_mem_clock_mhz" = "666" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end + chip cpu/intel/model_206ax + device cpu_cluster 0 on end - register "tcc_offset" = "5" # TCC of 95C - end + register "tcc_offset" = "5" # TCC of 95C end device domain 0 on diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index fef8992..2eeb745 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -11,15 +11,12 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - register "acpi_c1" = "CPU_ACPI_C3" - register "acpi_c2" = "CPU_ACPI_C6" - end + chip cpu/intel/model_206ax + device cpu_cluster 0 on end + + register "acpi_c1" = "CPU_ACPI_C3" + register "acpi_c2" = "CPU_ACPI_C6" end device domain 0 on diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a72b94f..bf87661 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -2,15 +2,11 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end + chip cpu/intel/model_206ax + device cpu_cluster 0 on end - register "acpi_c2" = "CPU_ACPI_C6" - register "acpi_c3" = "CPU_ACPI_DISABLED" - end + register "acpi_c2" = "CPU_ACPI_C6" + register "acpi_c3" = "CPU_ACPI_DISABLED" end device domain 0 on diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 2e5ee0f..44e7372 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -17,15 +17,11 @@ register "gpu_cpu_backlight" = "0x0000001a" register "gpu_pch_backlight" = "0x002e0000" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end + chip cpu/intel/model_206ax + device cpu_cluster 0 on end - register "acpi_c2" = "CPU_ACPI_C6" - register "acpi_c3" = "CPU_ACPI_DISABLED" - end + register "acpi_c2" = "CPU_ACPI_C6" + register "acpi_c3" = "CPU_ACPI_DISABLED" end device domain 0 on diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 20b1c9a..c6aa44c 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -17,15 +17,11 @@ register "gpu_cpu_backlight" = "0x00000ac8" register "gpu_pch_backlight" = "0x13120000" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end + chip cpu/intel/model_206ax + device cpu_cluster 0 on end - register "acpi_c2" = "CPU_ACPI_C6" - register "acpi_c3" = "CPU_ACPI_DISABLED" - end + register "acpi_c2" = "CPU_ACPI_C6" + register "acpi_c3" = "CPU_ACPI_DISABLED" end device domain 0 on diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index cd7b907..10aeb44 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -11,15 +11,11 @@ register "max_mem_clock_mhz" = "666" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end + chip cpu/intel/model_206ax + device cpu_cluster 0 on end - register "acpi_c1" = "CPU_ACPI_C3" - register "acpi_c2" = "CPU_ACPI_C6" - end + register "acpi_c1" = "CPU_ACPI_C3" + register "acpi_c2" = "CPU_ACPI_C6" end device domain 0 on diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 16fab6d..afa1e5b 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -1,19 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - device cpu_cluster 0 on - ops sandybridge_cpu_bus_ops - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end + chip cpu/intel/model_206ax + device cpu_cluster 0 on ops sandybridge_cpu_bus_ops end - register "acpi_c1" = "CPU_ACPI_C1" - register "acpi_c2" = "CPU_ACPI_C3" - register "acpi_c3" = "CPU_ACPI_C7" - end + register "acpi_c1" = "CPU_ACPI_C1" + register "acpi_c2" = "CPU_ACPI_C3" + register "acpi_c3" = "CPU_ACPI_C7" end - device domain 0 on ops sandybridge_pci_domain_ops end diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ad85d68..ee4ddc5 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -387,7 +387,6 @@ static void mc_gen_ssdt(const struct device *dev) { - generate_cpu_entries(dev); set_above_4g_pci(dev); } @@ -416,6 +415,7 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, + .acpi_fill_ssdt = generate_cpu_entries, }; struct chip_operations northbridge_intel_sandybridge_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Gerrit-Change-Number: 59316 Gerrit-PatchSet: 21 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: cpu/intel/sandybridge: Use enum for ACPI C states
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69292 ) Change subject: cpu/intel/sandybridge: Use enum for ACPI C states ...................................................................... cpu/intel/sandybridge: Use enum for ACPI C states Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_206ax/chip.h M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chipset.cb 7 files changed, 42 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 4fff04a..a46c7bf 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -3,10 +3,21 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC +/* Keep this in sync with acpi.c */ +enum cpu_acpi_level { + CPU_ACPI_DISABLED = 0, + CPU_ACPI_C1, + CPU_ACPI_C2, + CPU_ACPI_C3, + CPU_ACPI_C6, + CPU_ACPI_C7, + CPU_ACPI_C7S, +}; + struct cpu_intel_model_206ax_config { - int acpi_c1; /* ACPI C1 */ - int acpi_c2; /* ACPI C2 */ - int acpi_c3; /* ACPI C3 */ + enum cpu_acpi_level acpi_c1; + enum cpu_acpi_level acpi_c2; + enum cpu_acpi_level acpi_c3; int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 9255848..fef8992 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -17,8 +17,8 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "3" # ACPI(C1) = MWAIT(C3) - register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) + register "acpi_c1" = "CPU_ACPI_C3" + register "acpi_c2" = "CPU_ACPI_C6" end end diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 1bbbbfc..a72b94f 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -8,8 +8,8 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "0" # ACPI(C3) = MWAIT(C7) + register "acpi_c2" = "CPU_ACPI_C6" + register "acpi_c3" = "CPU_ACPI_DISABLED" end end diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 7cb6812..2e5ee0f 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -23,8 +23,8 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) - register "acpi_c3" = "0" + register "acpi_c2" = "CPU_ACPI_C6" + register "acpi_c3" = "CPU_ACPI_DISABLED" end end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 96a8ce8..20b1c9a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -23,8 +23,8 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) - register "acpi_c3" = "0" + register "acpi_c2" = "CPU_ACPI_C6" + register "acpi_c3" = "CPU_ACPI_DISABLED" end end diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ea164c4..cd7b907 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -17,8 +17,8 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "3" # ACPI(C1) = MWAIT(C3) - register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) + register "acpi_c1" = "CPU_ACPI_C3" + register "acpi_c2" = "CPU_ACPI_C6" end end diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index e7ade19..16fab6d 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -8,9 +8,9 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "CPU_ACPI_C1" + register "acpi_c2" = "CPU_ACPI_C3" + register "acpi_c3" = "CPU_ACPI_C7" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Gerrit-Change-Number: 69292 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: cpu/intel/model_206ax: Remove fake lapic device
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Arthur Heymans, Tristan Corrick, Angel Pons, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59316 ) Change subject: cpu/intel/model_206ax: Remove fake lapic device ...................................................................... Patch Set 20: (1 comment) File src/cpu/intel/model_206ax/acpi.c: https://review.coreboot.org/c/coreboot/+/59316/comment/76727ecd_6bae3fa9 PS18, Line 100: struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info; > Toplevel chip_info would be a pointer to different type of struct, northbridge_intel_sandybridge_config, though? Right. There is no way of knowing it's pointing to the right struct type (although you must really mess up devicetree for that) but it's never NULL. -- To view, visit https://review.coreboot.org/c/coreboot/+/59316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Gerrit-Change-Number: 59316 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Dec 2022 10:27:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/redrix: Adjust I2C3 timing for Touchscreen
by Chen Wisley (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70219 to review the following change. Change subject: mb/google/brya/var/redrix: Adjust I2C3 timing for Touchscreen ...................................................................... mb/google/brya/var/redrix: Adjust I2C3 timing for Touchscreen BUG=none TEST=build Change-Id: I01e98f55d37666d6a97e3723ed095ffad0bb15c0 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 19 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/70219/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 1d135d6..a000e8c 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -81,9 +81,12 @@ }, .i2c[3] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 170, + .scl_hcnt = 70, + .sda_hold = 40, + } }, .i2c[5] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/70219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e98f55d37666d6a97e3723ed095ffad0bb15c0 Gerrit-Change-Number: 70219 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai, Sukumar Ghorai. Hello Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai, Sukumar Ghorai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70196 to look at the new patch set (#3). Change subject: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low ...................................................................... mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SKL_S0_L` signal is `low` (while the system is in S0ix). Having `SLP_S0_GATE_R` configured to `high` makes `SYS_SLP_S0IX_L` remain `high` always and report the wrong system state to EC. BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce --- M src/mainboard/google/rex/variants/rex0/gpio.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Gerrit-Change-Number: 70196 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Hello Tarun Tuli, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70196 to look at the new patch set (#2). Change subject: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low ...................................................................... mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SKL_S0_L` signal is `low` while the system is in S0ix. Having `SLP_S0_GATE_R` configured to `high` makes `SYS_SLP_S0IX_L` remain `high` always and repo the wrong system state to EC. BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce --- M src/mainboard/google/rex/variants/rex0/gpio.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Gerrit-Change-Number: 70196 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP
by Kapil Porwal (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Sridhar Siricilla, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69978 ) Change subject: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Gerrit-Change-Number: 69978 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 09:30:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/zydron: Set touchpads to use probed flag
by Ren Kuo (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: David Wu, Tarun Tuli, Nick Vaccaro, Tyler Wang. Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70194 ) Change subject: mb/google/brya/var/zydron: Set touchpads to use probed flag ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a5ad5dc97cfaf1c10e7ff1e68b72af6add64c6 Gerrit-Change-Number: 70194 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 09:29:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2022